Display Clock Generator With Common Pulse for Motion Blur Control

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Solution Overview

Problem

Display devices experience motion blur due to overlapping previous and current images, and as resolution and driving frequency increase, the number of level shifters and input signals required for clock generation also increases, leading to complexity and inefficiency.

Innovation Solution

A clock generator that generates multiple clock signals with different phases, incorporating a common pulse based on an enable signal, and a gate driver that uses these signals to reduce the number of input signals and signal lines by sharing common signals among multiple level shifters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the resolution and driving frequency of the display device are increased, then the display quality is improved, but the number of level shifters and input signals increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidnumber of level shifters and input signals
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple clock signal generation functions into a single level shifter. The level shifter generates multiple clock signals with different phases (e.g., CLK1, CLK2, CLK3, CLK4) from a single input clock signal, eliminating the need for separate level shifters for each clock signal and reducing the overall number of input signals required.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The level shifter is designed to perform multiple functions simultaneously: it performs level shifting, generates multiple clock signals with different phases, and provides these signals to different gate drivers. This multi-functional design reduces the total number of components and input signals needed in the display device.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple level shifters are used to generate clock signals for high resolution, then clock signal generation capability is improved, but the number of control signals and signal lines increases

Engineering Contradiction:
Improveclock signal generation capabilityVSAvoidnumber of control signals and signal lines
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the clock signal generation capability of multiple level shifters into a single level shifter that can generate multiple clock signals internally. This reduces the number of control signals and signal lines that would otherwise be required to control multiple separate level shifters.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The level shifter segments the clock signal generation process into multiple phase-shifted outputs from a single input, allowing each output to be independently used by different gate drivers without requiring separate input signals for each.

Inventive Principle:
Principle #1Segmentation

3Reliability

If black frame insertion technology is applied to prevent motion blur, then image quality is improved, but the number of clock signals and control signals increases

Engineering Contradiction:
Improveimage qualityVSAvoidnumber of clock signals and control signals
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the clock signal generation for black frame insertion with the normal clock signal generation in a single level shifter. The level shifter generates additional clock signals with appropriate phases to control the black frame insertion timing, eliminating the need for separate control mechanisms and reducing the overall signal complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12567376B2Clock generator and display device including the same
Publication Date: 2026.03.03 SAMSUNG DISPLAY CO LTD
  • US12567376B2 patent drawing
  • US12567376B2 patent drawing
  • US12567376B2 patent drawing

AI summary

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.