Display Driving Circuit Layout for Interlaced Clock Coupling
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Solution Overview
Problem
The increased difficulty of layout design in interlaced scanning due to the necessity of preventing coupling between adjacent signal lines, which is exacerbated by the requirement of multiple signal lines for clock signal transmission.
Innovation Solution
A driving circuit comprising a control module, level conversion module, and pull-down module that generates and manages target clock signals using fewer initial clock signals, with the pull-down module selectively pulling down voltage on odd- or even-numbered clock signal lines to prevent coupling, thereby reducing the number of required signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interlaced scanning is implemented to multiply refresh rate, then refresh rate is improved, but layout design difficulty increases due to coupling prevention requirements between adjacent signal lines
Solution Approach 1:
The patent segments the clock signal transmission into two independent paths: one for odd-numbered clock signals and another for even-numbered clock signals. By using separate signal lines for odd and even clock signals, the design eliminates coupling issues between adjacent lines while maintaining the necessary signal transmission for interlaced scanning.
Solution Approach 2:
The patent applies different signal line configurations to different parts of the system. Specifically, odd-numbered clock signals use one set of signal lines while even-numbered clock signals use another set. This local differentiation allows each signal line to be optimized for its specific function, reducing coupling interference and simplifying layout design.
2Adaptability or versatility
If multiple signal lines are used for clock signal transmission in interlaced scanning, then signal transmission capability is improved, but layout design difficulty increases due to coupling prevention requirements
Solution Approach 1:
The patent divides the clock signal transmission into separate odd and even signal lines, allowing each line to be independently designed and laid out. This segmentation reduces the complexity of preventing coupling between adjacent lines while maintaining the ability to transmit multiple clock signals simultaneously.
Solution Approach 2:
The patent introduces a level conversion chip as an intermediary component that receives clock signals from the timing controller and converts them into the appropriate odd/even signal lines. This intermediary simplifies the layout by centralizing the signal conversion function, reducing the need for complex direct connections between the timing controller and display panel.
Data Source
AI summary
The present disclosure provides a driving circuit, a display panel and a display device. The driving circuit includes a control module, a level conversion module and a pull-down module. The control module is configured to output multiple initial clock signals to corresponding initial signal lines. The level conversion module is electrically connected to the initial signal lines, and is used to generate multiple target clock signals and output the multiple target clock signals to corresponding clock signal lines, the clock signal lines including odd-numbered clock signal lines and even-numbered clock signal lines. An input terminal of the pull-down module is electrically connected to the control module, an output terminal of the pull-down module is electrically connected to the clock signal lines, and the pull-down module is used to pull down voltage on the odd-numbered clock signal lines or pull down voltage on the even-numbered clock signal lines.