Display Clock Recovery Delay Compensation for Uniform Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In clock recovery circuits for displays, the difference in capacitance between delay units causes a disparity in delay time, which complicates clock recovery, especially during high-speed operations, and is affected by manufacturing processes.
Innovation Solution
A clock recovery circuit with a delay compensator that adjusts the capacitance of the first delay unit to match the capacitance of other delay units, using a capacitor bank and time digital converters to ensure uniform delay times across the multi-stage delay chain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a multi-stage delay chain is used in the clock recovery circuit, then the clock can be recovered without a separate oscillator, but the difference in capacitance between delay units causes delay time disparity that complicates clock recovery
Solution Approach 1:
The patent applies parameter changes by adjusting the capacitance values of specific delay units (particularly the first and last delay units) to compensate for their inherently different capacitance characteristics. By modifying the capacitance parameter of these boundary delay units to match the average capacitance of intermediate units, the delay times are equalized across all stages, enabling reliable clock recovery without requiring a separate oscillator.
2Device complexity
If uniform time constant is applied between delay units, then the delay chain operates simply, but the input side capacitance differs from inter-unit capacitance causing delay time difference
Solution Approach 1:
The patent implements local quality by applying different capacitance values to specific locations in the delay chain. The first and last delay units are assigned different capacitance values compared to the intermediate units, with the boundary units adjusted to match the average capacitance of the intermediate units. This localized adjustment ensures uniform delay times across all stages while maintaining the overall simplicity of the delay chain configuration.
3Speed
If high-speed operation is performed, then data transmission speed increases, but the difference in delay time causes difficulty in recovering data
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the capacitance values of the first and last delay units before the clock recovery process begins. By setting these boundary delay units to have capacitance values that match the average of the intermediate units, the delay times are equalized in advance. This preliminary configuration ensures that even during high-speed operations, the uniform delay times across all stages enable reliable data recovery without requiring additional real-time adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution stabilizes the recovery of clock and data by compensating for delay time differences, ensuring reliable data recovery in high-speed operations and accommodating manufacturing variations.
Implementation Method 1
a delay compensator configured to control capacitance of an input side of a first delay unit to compensate for a difference in delay time between a first delay time of the first delay unit and a second delay time of a second delay unit
Data Source
AI summary
The present disclosure discloses a clock recovery circuit for a display, which recovers a clock from a clock data signal. The clock recovery circuit includes a clock recoverer configured to generate delayed clocks using a multi-stage delay chain including delay units; and a delay compensator configured to control a first delay time of a first delay unit to be the same as a second delay time of remaining delay units. The clock recovery circuit may compensate for a difference in delay time between the first delay time and the second delay time.