Display Driving Circuit Clock Calibration for Frequency Drift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In MIPI DSI display devices, the internal clock signal frequency can drift due to temperature changes or process variations, especially in command mode where timing information is not provided, making it challenging to maintain frequency precision without adjustment mechanisms.
Innovation Solution
A calibration module within the display driving circuit that generates a calibration signal by counting pulses of both the internal and reference clock signals, allowing the circuit to adjust the internal clock signal frequency based on predefined conditions, ensuring it aligns with the standard frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the display device operates in command mode without timing information from MIPI host, then the device structure is simplified, but the internal clock signal frequency cannot be calibrated and drifts occur
Solution Approach 1:
The display device performs self-calibration of the internal clock signal frequency by counting pulses of both the internal clock signal and reference clock signal, and automatically generating calibration signals to adjust the internal clock circuit when drift is detected, without requiring external timing information from the MIPI host
Solution Approach 2:
The system establishes a feedback loop where the calibration module continuously monitors the internal clock signal frequency by comparing it with the reference clock signal, and automatically generates calibration signals to adjust the internal clock circuit when frequency drift exceeds predefined thresholds
2Ease of operation
If the internal clock signal frequency is not adjusted, then the device operation is simple, but frequency drift occurs due to temperature change or process variation
Solution Approach 1:
The display device performs self-calibration of the internal clock signal frequency by counting pulses of both the internal clock signal and reference clock signal, and automatically generating calibration signals to adjust the internal clock circuit when drift is detected, without requiring external timing information from the MIPI host
Solution Approach 2:
The system dynamically adjusts the frequency parameter of the internal clock signal by applying calibration signals to the internal clock circuit, changing its operating parameters to compensate for temperature changes and process variations
3Measurement precision
If calibration module is added to enable self-adjustment, then frequency precision is maintained, but device complexity increases
Solution Approach 1:
The calibration module is designed to perform multiple functions: counting pulses of the internal clock signal, counting pulses of the reference clock signal, comparing the counts to detect frequency drift, and generating calibration signals to adjust the internal clock circuit, thereby reducing the need for separate dedicated circuits for each function
Solution Approach 2:
The calibration module integrates the pulse counting function, frequency comparison function, and clock signal adjustment function into a single unified circuit block, combining multiple previously separate functions into one compact structure
Data Source
AI summary
A display driving circuit, a calibration module, and an associated calibration method are provided. The display driving circuit includes an internal clock circuit and the calibration module. The internal clock circuit generates an internal clock signal. The calibration module includes a counting circuit and a trimming circuit. The counting circuit counts pulses of a reference clock signal to generate a detected reference-clock count and counts pulses of the internal clock signal to generate a detected internal-clock count. The trimming circuit generates a calibration signal to adjust frequency of the internal clock signal when a predefined condition is satisfied. The predefined condition is related to comparison between a first preset count and one of the detected reference-clock count and the detected internal-clock count.