Display Clock Gating for Repeated Pixel Data Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Increased power consumption in display devices due to higher data transfer speeds, particularly in mobile devices, is a challenge as it affects battery life and efficiency.
Innovation Solution
Implementing a clock gating mechanism in the display device that detects repeated pixel data patterns and gates the clock signal during power-saving periods, reducing data sampling during these periods to conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transfer speed is increased to improve image quality and processing capability, then image quality and processing power are improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing clock gating that selectively enables or disables clock signals based on whether data changes are detected. The clock signal is periodically activated only when necessary for data updates, rather than continuously running, thereby reducing power consumption while maintaining required data transfer speeds for image quality and processing performance.
2Use of energy by moving object
If clock gating is implemented to reduce power consumption, then power consumption is reduced, but data transfer efficiency may be affected
Solution Approach 1:
The patent employs feedback mechanisms by monitoring data change signals to control clock gating. When data changes are detected, the system receives feedback and activates the clock signal accordingly. This feedback-based control ensures that data transfer efficiency is maintained during updates while achieving power savings during static periods, resolving the contradiction between power reduction and transfer efficiency.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A display device includes a display panel including a plurality of pixels, a controller configured to output image data and a gated clock signal, the image data including a plurality of pixel data for the plurality of pixels, and a data driver configured to receive the image data and the gated clock signal from the controller, and to sample the image data in response to the gated clock signal. The controller detects a repeated data pattern where same pixel data is repeated in the image data, generates a clock enable signal having an off level in a period in which the repeated data pattern is transferred, and gates an input clock signal in response to the clock enable signal to produce the gated clock signal.