Display Device Clock Signal Load Balancing via Grounding Resistors
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Solution Overview
Problem
Existing ultra-high resolution display devices suffer from display defects such as black and white horizontal lines due to in-plane load differences between clock signal lines, which affect display quality and customer experience, and current manufacturing process adjustments do not completely solve these issues, leading to decreased product yield and efficiency.
Innovation Solution
A display device design that includes a processor, timing controller, circuit board, display panel, clock signal lines, grounding resistors, and gate drivers, where the grounding resistors connected to the clock signal lines on the circuit board reduce voltage levels and eliminate load differences, optimizing the circuit design to prevent black and white horizontal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of the display device increases to achieve large size and ultra-high resolution, then the display resolution and area are improved, but the in-plane load increases causing black and white horizontal lines
Solution Approach 1:
The patent applies local quality by introducing grounding resistors at specific locations along the clock signal lines to differentially adjust the load of individual signal lines. This localized intervention compensates for the in-plane load differences that arise in large-size displays, thereby eliminating the black and white horizontal lines while preserving the overall large display area and ultra-high resolution capabilities
2Object-generated harmful factors
If manufacturing process is adjusted to reduce in-plane load difference between clock signal lines, then the black and white horizontal lines are reduced, but product yield and production efficiency decrease
Solution Approach 1:
The patent replaces the mechanical/manufacturing process adjustment approach with an electrical/circuit solution by introducing grounding resistors. This substitution allows for precise electrical load balancing of clock signal lines without requiring complex manufacturing process modifications, thereby eliminating black and white horizontal lines while maintaining high product yield and production efficiency
3Object-generated harmful factors
If grounding resistors are introduced to adjust clock signal line load, then the load difference is eliminated, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by selectively adjusting the resistance values of grounding resistors connected to different clock signal lines. By optimizing the resistance parameters, the patent achieves load balancing across all clock signal lines, eliminating black and white horizontal lines while keeping the circuit design relatively simple and manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively eliminates the load difference between clock signal lines, improving image quality, product yield, and production efficiency by reducing voltage levels and enhancing current flow, thereby eliminating black and white horizontal lines.
Implementation Method 1
a plurality of grounding resistors disposed on the circuit board, wherein each of the grounding resistors is connected to a corresponding clock signal line, and is configured to reduce a voltage value of the high level of the initial clock signal to obtain an adjusted clock signal
Data Source
AI summary
A display device is provided, including a circuit board, a display panel, a plurality of clock signal lines, and a plurality of grounding resistors. Each clock signal line extends from the circuit board to a non-display area of the display panel. The plurality of grounding resistors are disposed on the circuit board. Each grounding resistor is connected to a corresponding clock signal line, and is configured to reduce a voltage value of high level of the clock signal.