Display Panel Clock Line Layout for Lower RC Delay
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Solution Overview
Problem
In display devices, the large resistance of clock signal lines and parasitic capacitance lead to signal distortion and prolonged falling times of signals provided by shift register units.
Innovation Solution
A display panel design that includes a driving circuit and a signal line with multiple main signal sub-lines, where some sub-lines are directly coupled to the driving circuit and others are indirectly coupled, reducing resistance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal line is used to provide signals to the driving circuit, then the device complexity is reduced, but the resistance and parasitic capacitance increase causing signal distortion and long falling time
Solution Approach 1:
The patent divides the single clock signal line into multiple parallel main signal sub-lines (first, second, third, fourth sub-lines). Each sub-line directly provides clock signals to specific shift register units, segmenting the signal transmission path to reduce resistance and parasitic capacitance while maintaining structural organization.
Solution Approach 2:
The patent transitions from a one-dimensional single signal line to a two-dimensional parallel network of multiple sub-lines. This dimensional expansion allows simultaneous signal distribution to multiple destinations, reducing the RC delay of individual paths while maintaining overall system complexity through structured arrangement.
2Reliability
If multiple main signal sub-lines are used to reduce resistance and parasitic capacitance, then signal transmission quality improves, but the device complexity increases
Solution Approach 1:
The patent merges multiple parallel main signal sub-lines into a unified clock signal distribution network. All sub-lines originate from common first and second ends and are electrically coupled to the same driving circuit, combining their effects to reduce overall resistance and parasitic capacitance while presenting a structured, manageable configuration.
Solution Approach 2:
Each main signal sub-line serves multiple functions: providing clock signals to specific shift register units, reducing RC delay through parallel paths, and collectively forming a robust signal distribution network. The indirect-coupled sub-lines also serve to further reduce parasitic capacitance by not being directly connected to the driving circuit output.
3Speed
If all main signal sub-lines are directly coupled to the driving circuit, then signal strength is maintained, but parasitic capacitance increases causing signal distortion
Solution Approach 1:
The patent applies different coupling configurations to different main signal sub-lines based on their specific transmission needs. Direct-coupled sub-lines (first and second) maintain strong signal strength for critical paths, while indirect-coupled sub-lines (third and fourth) reduce parasitic capacitance for paths where signal regeneration is acceptable, creating localized optimization throughout the network.
Solution Approach 2:
The indirect-coupled main signal sub-lines act as intermediary pathways that reduce parasitic capacitance loading on the driving circuit. By routing these sub-lines through other sub-lines rather than direct connection, the system mediates between the need for signal strength and the need to minimize capacitive loading, preventing signal distortion.
Data Source
AI summary
A display panel includes a driving circuit and a signal line. The signal line includes at least two main signal sub-lines each including a first end and a second end, the first ends of the at least two main signal sub-lines are electrically coupled to each other, and the second ends thereof are electrically coupled to each other. N main signal sub-lines in the at least two main signal sub-lines are directly electrically coupled to the driving circuit. Each of the N main signal sub-lines is a direct-coupled main signal sub-line, and a main signal sub-line in the at least two main signal sub-lines other than the direct-coupled main signal sub-lines is an indirect-coupled main signal sub-line which is not directly electrically coupled to the driving circuit but electrically coupled to the driving circuit via the direct-coupled main signal sub-line, where N is a positive integer.