Display Panel Clock Line Segmentation for Luminance Uniformity
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Solution Overview
Problem
Luminance deviations occur between different areas of a display panel due to clock signal delays, which are caused by varying RC delays in the gate drivers, leading to inconsistent display quality.
Innovation Solution
The display device separates clock lines based on the display panel's areas and applies clock signals with different voltage levels or gate-on times through these lines to mitigate luminance deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock line is used for all gate drivers, then the device complexity is reduced, but luminance deviations occur due to varying RC delays across different areas
Solution Approach 1:
The display panel is divided into multiple areas (first area and second area), and separate clock lines (first clock line and second clock line) are provided for each area. This segmentation allows independent optimization of clock signal parameters for different regions, compensating for RC delay variations and achieving uniform luminance across the display panel.
2Manufacturing precision
If clock signals with different voltage levels are applied to different areas, then luminance uniformity is improved, but device complexity increases
Solution Approach 1:
Different clock signal parameters (voltage levels or gate-on times) are applied to different areas of the display panel according to their specific RC delay characteristics. The first clock signal is applied to the first area and the second clock signal is applied to the second area, with at least one parameter differing between the two signals. This local optimization ensures uniform luminance output across the entire display panel while managing complexity through targeted parameter adjustment.
Data Source
AI summary
A display device includes a display panel including a first area and a second area in which a plurality of pixels are arranged; a plurality of gate drivers disposed in the first area and the second area; a first clock line connected to at least one first gate driver disposed in the first area; a second clock line connected to at least one second gate driver disposed in the second area; and a level shifter configured to generate a first clock signal and a second clock signal to be applied to each of the first clock line and the second clock line, respectively, wherein the first clock signal and the second clock signal have different voltage levels or gate-on times.