Display Timing Control Using Internal Clock Phase Calibration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face challenges in reducing power consumption at the timing controller and source driver, necessitating improved methods to lower complexity and cost while maintaining accurate display control.
Innovation Solution
A display control method and device that generates an internal clock signal without relying on external clock signals, using phase-shifted internal signals to reduce feedback burden and simplify panel design, applicable across various panel sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If external clock signals are used for display control, then timing accuracy is maintained, but device complexity and power consumption increase
Solution Approach 1:
The display control device generates its own internal clock signal autonomously without requiring external clock inputs. The controller internally produces the clock signal needed for data reception and processing, making the system self-sufficient and reducing external component requirements while maintaining timing accuracy through internal phase adjustment mechanisms
Solution Approach 2:
The patent extracts and removes the external clock signal requirement from the system. By eliminating the need for external clock inputs and replacing them with internally generated clock signals, the system reduces panel component complexity while maintaining functional equivalence through the internal clock generation and phase adjustment mechanism
2Measurement precision
If multiple feedback data receptions are performed for phase adjustment, then timing precision is improved, but processing time increases
Solution Approach 1:
The system performs preliminary phase adjustment by receiving multiple feedback data packets and adjusting the internal clock phase in advance before normal operation begins. This preliminary action ensures that the internal clock is properly synchronized with the data input, eliminating the need for repeated adjustments during operation and reducing overall setup time
Solution Approach 2:
The patent implements a feedback mechanism where the controller receives feedback data from the driver IC, compares it with expected values, and adjusts the internal clock phase accordingly. This closed-loop feedback process enables automatic timing synchronization, improving precision while streamlining the setup procedure through automated adjustment rather than manual configuration
Data Source
AI summary
Disclosed is a display control method according to embodiments. The display control method includes: transmitting a command for sensing to a driver integrated circuit (DIC); receiving feedback data including a transfer start indicator from the DIC; generating an internal clock signal and shifting a phase of the internal clock signal; checking the transfer start indicator of the feedback data based on the phase-shifted internal clock signal; and repeating receiving the feedback data, generating the internal clock signal, and shifting the phase of the internal clock signal a predetermined number of times. A center value may be determined from among values corresponding to numbers of times that the transfer start indicator is received while repeating the reception, the generation, and the phase shift the predetermined number of times.