Display Clock Generator With Phase-Shifted Pre-Clocks
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Solution Overview
Problem
Existing clock generators and display devices face challenges in reducing wiring complexity while maintaining high-frequency performance, leading to increased costs.
Innovation Solution
A clock generator design that includes a first clock generation circuit, serial wiring for clock, data, and timing control signals, and a second clock generation circuit capable of generating pre-clocks with phase shifts, along with a clock adjustment circuit that fine-tunes the output clock using the timing control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of wirings is reduced to transmit clock through high-frequency serial interface, then wiring complexity is reduced, but cost increases due to requirement for high-performance clock generator and level shifter
Solution Approach 1:
The clock generation function is divided into two separate circuits: a first clock generation circuit that outputs the clock signal, and a second clock generation circuit that generates pre-clocks with phase shifts. This segmentation allows each circuit to operate at lower performance levels, reducing the need for expensive high-performance components while maintaining the ability to generate multiple phase-shifted clock signals through the phase shifting mechanism.
Solution Approach 2:
The second clock generation circuit performs preliminary phase shifting to generate pre-clocks before the final clock adjustment. By pre-shifting the phases in the second clock generation circuit and then making fine adjustments in the clock adjustment circuit, the system achieves precise clock timing without requiring the first clock generation circuit to handle all phase adjustment requirements, thereby reducing overall component performance requirements and cost.
2Reliability
If high-performance clock generator and level shifter are used, then clock transmission quality is improved, but cost increases
Solution Approach 1:
The clock generation system is segmented into multiple functional blocks with distributed phase shifting capabilities. The first clock generation circuit generates the base clock, the second clock generation circuit provides coarse phase shifting, and the clock adjustment circuit provides fine tuning. This distribution of functionality allows each component to be designed with relaxed performance specifications, reducing overall system cost while maintaining clock transmission quality.
Solution Approach 2:
The system changes the approach from using high-performance components to achieving clock quality through parameter control. By controlling the phase shift amounts in the second clock generation circuit and the timing adjustment parameters in the clock adjustment circuit, the system achieves precise clock timing without requiring components with inherently high performance specifications, thereby reducing cost.
3Adaptability or versatility
If phase-shifting capability is added to generate multiple pre-clocks, then design flexibility is improved, but device complexity increases
Solution Approach 1:
The phase shifting functionality is merged into the second clock generation circuit, which already exists for generating clock signals. By combining phase shifting with the existing clock generation function, the patent avoids adding separate phase shifting circuits, thereby reducing overall device complexity while still providing the ability to generate multiple phase-shifted pre-clocks for different pixel driving methods.
Data Source
AI summary
The present disclosure relates to a clock generator and a display device including the same. The clock generator includes a first clock generation circuit configured to output a clock, data, and a timing control signal; a first wiring through which the clock is serially transmitted; a second wiring through which the data is serially transmitted; a third wiring through which a pulse of the timing control signal is serially transmitted; a second clock generation circuit connected to the first clock generation circuit through the first wiring, the second wiring, and the third wiring and configured to generate pre-clocks in which phases are sequentially shifted based on the data and the clock; and a clock adjustment circuit configured to receive the pulse of the timing control signal and the pre-clock and output an output clock.