Display Engine Clock Switching Without PLL Shutdown
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Solution Overview
Problem
When an external display is added or its configuration is modified, existing systems often experience undesirable issues such as audio loss and display tearing or blinking, and current solutions like operating the display engine at its fastest clock result in high power consumption or disrupt the user experience.
Innovation Solution
The technique involves dynamically changing the clock frequency of the display engine by reprogramming the core display clock phase-locked loop (PLL) without turning it off and on, using a divide-by-2 divider or other ratios to adjust frequencies, allowing the system to operate at optimal frequencies and avoid power wastage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display engine operates at its fastest clock frequency to avoid display tearing and audio loss, then display stability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by monitoring display configuration changes and adjusting the display engine clock frequency in real-time. When display configuration changes are detected, the system dynamically changes the clock frequency to prevent display tearing and audio loss, rather than operating at a fixed maximum frequency. This dynamic adaptation resolves the contradiction by providing high frequency only when necessary for stability.
Solution Approach 2:
The system changes the operational parameters of the display engine by adjusting the clock frequency based on display configuration state. The patent uses phase-locked loop (PLL) reprogramming to change the clock frequency parameter dynamically, allowing the display engine to operate at optimal frequencies for different display configurations, thus reducing power consumption while maintaining display stability when needed.
2Adaptability or versatility
If the display engine clock frequency is changed by turning the PLL off and on, then frequency adjustment is achieved, but display blinking and audio loss occur
Solution Approach 1:
The patent applies preliminary action by reprogramming the PLL frequency settings before actually changing the display configuration. The system prepares the new clock frequency in advance, then transitions to it smoothly, ensuring that the display engine maintains continuous operation without blinking or audio loss. This preliminary preparation allows frequency adjustment while preserving display continuity.
Solution Approach 2:
The system maintains continuous operation of the display engine during frequency transitions. Instead of turning the PLL off and on (which causes interruptions), the patent implements continuous frequency adjustment by keeping the PLL locked and smoothly transitioning between frequency states. This ensures the useful action of display rendering continues without interruption, preventing display blinking and audio loss.
3Adaptability or versatility
If the display engine operates at maximum clock frequency to support multiple displays, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic frequency adjustment based on the number and configuration of active displays. When multiple displays are connected, the system dynamically increases the clock frequency to support the additional display load. When displays are removed or resolution is reduced, the frequency is dynamically decreased to save power. This dynamic adaptation allows multi-display support while avoiding unnecessary power consumption at maximum frequency when not needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates audio loss and display issues while saving power, improving system performance by dynamically adjusting the display engine clock frequency during external display configuration changes.
Implementation Method 1
reprogram the core display clock phase-locked loop (PLL) without turning it off and on
Data Source
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AI summary
Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back on again at all.