Display Clock Signal Separation for Luminance Uniformity

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Solution Overview

Problem

Luminance non-uniformity in display apparatuses caused by load differences in gate drivers, particularly when openings or notches are formed in the display panel for embedding optical devices, leads to luminance deviations in sub-display areas compared to main display areas.

Innovation Solution

A display apparatus and driving method that separate sub-clock and main clock signals to control sub-display and main display areas, varying the pulse width of the sub-clock signal based on the shape of the opening to compensate for luminance differences, thereby adjusting the sampling time and data voltage charging rate of subpixels in the sub-display area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If an opening (hole or notch) is formed in the display area for embedding optical devices, then the display apparatus can integrate optical functions, but luminance non-uniformity occurs in the sub-display area compared to the main display area

Engineering Contradiction:
Improveintegration of optical devicesVSAvoidluminance uniformity
Core Design Contradiction:
Adaptability or versatilityVSIllumination intensity

Solution Approach 1:

The patent applies local quality by differentiating the clock signal parameters between the sub-display area (with opening) and main display area. Specifically, the pulse width of the clock signal is adjusted locally in the sub-display area to compensate for the luminance non-uniformity caused by the opening, while the main display area maintains standard parameters. This localized parameter adjustment ensures each area receives appropriate driving conditions for its structural characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the temporal parameters of the clock signal (pulse width, sampling time) to compensate for the structural difference introduced by the opening. By varying the pulse width of the clock signal applied to the sub-display area, the data voltage charging time is adjusted, thereby balancing the luminance output between areas with and without openings.

Inventive Principle:
Principle #35Parameter changes

2Illumination intensity

If the pulse width of the sub-clock signal is varied to compensate for luminance differences, then luminance uniformity is improved, but the complexity of the driving circuit increases

Engineering Contradiction:
Improveluminance uniformityVSAvoiddriving circuit complexity
Core Design Contradiction:
Illumination intensityVSDevice complexity

Solution Approach 1:

The patent segments the clock signal into separate sub-clock and main clock signals, allowing independent parameter control for different display areas. The sub-clock signal is specifically designed with variable pulse width to address the sub-display area requirements, while the main clock signal maintains standard parameters for the main display area. This segmentation enables targeted parameter adjustment without affecting the entire display system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic parameter adjustment by varying the pulse width of the sub-clock signal based on the specific requirements of the sub-display area. This dynamic adjustment allows the driving circuit to adapt to the structural differences caused by the opening, compensating for luminance non-uniformity through real-time parameter modification rather than static design.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11875730B2Display apparatus and driving method thereof
Publication Date: 2024.01.16 LG DISPLAY CO LTD
  • US11875730B2 patent drawing
  • US11875730B2 patent drawing
  • US11875730B2 patent drawing

AI summary

A display apparatus includes a display panel including a sub-display area including an opening and a main display area including no opening, a gate driver supplying a gate signal to the display panel, and a driver controlling the gate driver, wherein the driver separates a sub-clock signal for controlling the sub-display area and a main clock signal for controlling the main display area and varies a pulse width of the sub-clock signal.