Display Device Clock Recovery During Active Data Periods
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Solution Overview
Problem
Existing clock recovery circuits in display devices only operate during the vertical blanking period and fail to recover the clock signal during active data periods, leading to display defects due to electrostatic discharge or other catalysts, which persist until the next clock training pattern is supplied.
Innovation Solution
A display device and driving method that allow immediate clock signal recovery during both vertical blanking and active data periods by using a timing controller and data driver to generate and re-generate the clock signal based on feedback signals, with phase signals and detectors to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock recovery circuit operates only during the vertical blanking period, then the device complexity is reduced and electromagnetic noise is minimized, but the reliability deteriorates because the clock signal cannot be recovered during active data periods when electrostatic discharge may occur
Solution Approach 1:
The system performs preliminary clock signal recovery during the vertical blanking period before active data transmission begins. This preliminary action ensures the clock signal is already locked and stable before electrostatic discharge risks occur during active periods, preventing display defects without requiring continuous complex recovery operations
Solution Approach 2:
A feedback mechanism continuously monitors the lock status of the clock signal during active data periods. When lock failure is detected (indicating electrostatic discharge or other catalysts have affected the signal), the system automatically triggers re-supply of the clock training pattern to restore synchronization, ensuring reliable operation without permanent display defects
2Reliability
If the clock training pattern is continuously supplied during active data periods, then the clock signal recovery capability is improved, but the loss of time for actual data transmission increases and productivity deteriorates
Solution Approach 1:
The clock training pattern is supplied periodically rather than continuously - specifically during vertical blanking periods and only when lock failure is detected during active periods. This periodic supplementation maintains clock synchronization reliability while maximizing active data transmission time, as the system operates in normal mode during active periods and only intervenes when necessary
Solution Approach 2:
The clock training function is extracted from continuous operation and separated into specific trigger conditions - namely, lock failure detection during active periods. This allows the system to maintain high productivity during normal active data transmission while providing targeted clock recovery intervention only when synchronization problems occur
3Reliability
If feedback signal transmission is implemented during active data periods, then the ability to detect and respond to clock lock failure is improved, but the device complexity and electromagnetic noise generation increase
Solution Approach 1:
A feedback signal line is implemented between the data driver and timing controller to transmit clock lock status information during active data periods. This feedback mechanism enables real-time detection of electrostatic discharge effects and triggers appropriate recovery actions, improving reliability despite the added electromagnetic noise from the feedback signaling
Solution Approach 2:
The feedback signal acts as an intermediary communication channel that allows the data driver to inform the timing controller of lock status without requiring direct intervention in the data transmission path. This intermediary approach enables monitoring and response to clock issues while minimizing interference with primary data transmission and reducing overall electromagnetic noise
Data Source
AI summary
A display device may include a timing controller, a data driver and a plurality of pixels. The timing controller supplies a clock training pattern over a data/clock signal line in a first time period, and supplies pixel/control data over the data/clock signal line in a second time period. The data driver generates a clock signal, using the clock training pattern, in the first period, and generate a plurality of data voltages based on the plurality of pixel data, using the clock signal, in the second period. The plurality of pixels receive the plurality of data voltages and emit corresponding light. During the second period, the data driver outputs a feedback signal to the timing controller indicating that the locking of the clock signal has failed. The timing controller re-supplies the clock training pattern in response to the feedback signal.