Display Interface Clock Recovery for Multi-Drop Signal Timing
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Solution Overview
Problem
The multi-drop method used for signal transmission in display devices leads to degraded signal transmission characteristics due to branching, requires additional pins for separate clock and signal lines, and results in insufficient timing margins due to length differences between these lines.
Innovation Solution
A display device with a timing controller that interfaces with data driving circuits through multiple interfaces, utilizing a clock recovery circuit, phase conversion clock signals, and a clock phase calibrator to recover and calibrate the clock signal, eliminating the need for a separate clock line pair by using the recovered clock signal for sampling, thereby improving signal transmission characteristics and simplifying the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the multi-drop method is used for signal transmission, then the interface can be simplified and pins reduced, but the signal transmission characteristic is degraded due to branching
Solution Approach 1:
The patent divides the interface into two separate interfaces: a first interface for transmitting data signals and a second interface for transmitting sensing signals. This segmentation eliminates the multi-drop configuration that caused signal degradation while maintaining interface simplicity. Each interface is dedicated to specific signal types, preventing the stub effects that occur when multiple branches diverge from a main line.
2Reliability
If a separate clock line pair is used for transmitting the sensing signal, then the transmission can be reliable, but the number of pins to be coupled increases
Solution Approach 1:
The patent combines the clock signal transmission function with the data signal transmission function by embedding the clock signal within the data signal stream. The clock recovery circuit extracts the clock signal from the data signal, eliminating the need for separate clock line pairs while maintaining reliable timing for sensing signal transmission.
Solution Approach 2:
The first interface is designed to serve multiple functions: it transmits both data signals and embedded clock signals. This multi-functionality allows the same physical interface to handle both data transmission and clock synchronization, reducing the total number of pins required while ensuring reliable signal transmission.
3Loss of time
If separate clock and signal line pairs are used, then timing can be controlled, but the difference in length between lines causes insufficient timing margin
Solution Approach 1:
By merging the clock signal into the data signal transmission path, the patent ensures that the clock and data signals travel through the same physical medium. This eliminates length differences between separate clock and data lines, ensuring that timing margins are sufficient without requiring complex line length matching or additional timing control circuitry.
Data Source
AI summary
A display device may extract an edge of a data signal based on the data signal and phase conversion clock signals, extract a phase of the data signal based on the edge, and generate a clock phase calibration signal based on the phase of the data signal. The display device may calibrate a phase of a clock signal using the clock phase calibration signal that has a phase corresponding to the phase of the clock signal, thereby improving transmission characteristic of the signal.