Display Clock Synchronization for Dynamic Refresh Power Reduction
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Solution Overview
Problem
Dynamic refresh rate techniques between a source device and a display device often require clocks to operate at their maximum frequencies, leading to excessive power consumption and potential artifacts like stuttering and blur, especially when the refresh rates mismatch.
Innovation Solution
The system coordinates source and display device clock values to reduce power consumption by adjusting refresh rates based on application types, using detection circuitry to identify application demands and modify clock frequencies accordingly, synchronizing the refresh rates to avoid artifacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clocks operate at maximum frequencies to maintain dynamic refresh rate, then display performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by detecting application types and modifying source and pixel clock frequencies accordingly. The system transitions from static maximum frequency operation to dynamic frequency scaling, where clocks operate at optimal frequencies based on actual application demands rather than always running at maximum rates.
Solution Approach 2:
The patent changes the operational parameters (clock frequencies) of the display system based on detected application types. By modifying the source clock and pixel clock frequencies from fixed maximum values to variable values matched to application requirements, the system reduces power consumption while maintaining adequate display performance for each application category.
2Speed
If clocks operate at maximum frequencies, then display performance is maintained, but visual artifacts like stuttering and blur occur
Solution Approach 1:
The system dynamically adjusts clock frequencies to match application-specific refresh rate requirements, preventing the mismatch between source and display refresh rates that causes visual artifacts. By making refresh rates adaptive rather than fixed, the system eliminates stuttering and blur while maintaining smooth performance where needed.
Solution Approach 2:
The patent employs feedback through application type detection to inform clock frequency adjustments. The detection circuitry provides information about the running application, which feeds back to the clock control mechanism, enabling it to select appropriate refresh rates that prevent visual artifacts for each application category.
3Use of energy by moving object
If refresh rates are reduced for power savings, then power consumption decreases, but display performance may deteriorate
Solution Approach 1:
The patent applies different clock frequency settings tailored to specific application types. Instead of uniformly reducing refresh rates across all applications, the system provides localized optimization where each application category receives the appropriate refresh rate for its needs, preventing performance deterioration while achieving power savings where possible.
Solution Approach 2:
The system changes operational parameters (clock frequencies) based on application-specific requirements rather than applying a uniform reduction. By matching refresh rates to application demands, the system avoids performance deterioration in applications that require higher rates while reducing power consumption in applications that can tolerate lower rates.
Data Source
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AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed to reduce dynamic refresh rate power consumption. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to modify a value of a source clock based on a detected application type, generate a pixel clock value change request based on the application type, cause transmission of the pixel clock value change request to a display, and cause transmission of pixels to the display at the modified source clock value.