Display Driver Clock Calibration for High Refresh Rate Switching
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Solution Overview
Problem
Current display technologies face inefficiencies in clock calibration, particularly during the blanking phase, which can impact the refresh rate and display quality, as existing methods require lengthy re-calibration processes when adjusting the clock frequency, leading to potential delays in displaying the next frame of image.
Innovation Solution
A method and device for clock calibration that involves sending a configuration instruction and clock calibration signals to a target driving chip, allowing it to adjust its local clock frequency, with the reference clock frequency set close to the target frequency, enabling rapid calibration and meeting high refresh rate requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a lengthy re-calibration process is used to adjust clock frequency, then calibration accuracy is improved, but the refresh rate and display performance deteriorate due to delays
Solution Approach 1:
The patent applies preliminary action by pre-calibrating the clock frequency during the initialization phase before actual display operations begin. The controller pre-adjusts the clock frequency to match the target frequency, so that when refresh rate changes are needed, the calibration is already complete and no lengthy re-calibration is required during operation. This resolves the contradiction by performing the time-consuming calibration work in advance, allowing fast refresh rates during actual display while maintaining calibration accuracy.
2Adaptability or versatility
If clock frequency is adjusted during blanking phase, then display adaptability is improved, but calibration time exceeds available blanking period causing frame display delays
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable and adaptable during operation. The controller can dynamically change the clock frequency based on display requirements while using multiple calibration circuits to ensure the adjustment can be completed within the blanking phase time constraint. This resolves the contradiction by enabling display adaptability through dynamic frequency adjustment while managing the time loss through efficient use of calibration resources.
Solution Approach 2:
The patent applies segmentation by dividing the calibration function into multiple independent calibration circuits, each capable of handling different frequency adjustment scenarios. This segmentation allows parallel processing of calibration tasks and enables the system to complete frequency adjustments within the limited blanking phase duration, preventing frame display delays while maintaining display adaptability.
3Adaptability or versatility
If multiple clock calibration circuits with different frequencies are used, then calibration coverage and adaptability are improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing calibration circuits that can serve multiple functions. The multiple clock calibration circuits are configured to handle different frequency ranges and calibration scenarios, making each circuit multi-functional. This reduces the overall system complexity compared to having dedicated circuits for each specific frequency, while still providing comprehensive calibration coverage and adaptability for different display requirements.
Data Source
AI summary
A method for clock calibration is provided. In the technical solution according to the present disclosure, a target driving chip includes a plurality of clock calibration circuits, wherein each of the clock calibration circuits is configured with one clock frequency. Prior to sending a clock calibration signal, a controller sends a reference clock frequency to a driving chip over a configuration instruction, such that the driving chip determines a target clock calibration circuit for clock calibration based on the configuration instruction.