Display Device Clock Line Segmentation for Charge Transfer
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Solution Overview
Problem
Display devices face challenges in maximizing charge transfer efficiency between the clock line and gate driver while minimizing heat generation in non-display areas, as existing technologies do not effectively optimize the structural layout and connectivity of clock and connection members.
Innovation Solution
The display device incorporates a substrate with a gate line, a gate driver, a clock-signal structure, and a connection structure, featuring clock members, linking members, and connection members arranged in a specific zigzag pattern with alternating orientations, and a conductive layer contacting these members through strategically placed contact holes to enhance charge transfer and reduce heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock line and connection line are arranged in a conventional layout, then the device complexity is low, but the charge transfer efficiency between clock line and gate driver is insufficient
Solution Approach 1:
The clock line is divided into multiple clock members (first clock member, second clock member, etc.) that are spatially separated and connected through linking members. This segmentation allows each clock member to be optimally positioned for charge transfer to different gate lines, improving overall charge transfer efficiency while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent introduces vertical layering with multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) to arrange clock members and connection members in three-dimensional space. This dimensional expansion allows clock members to extend in different directions (first direction, second direction) without increasing planar complexity, enabling efficient charge transfer paths while reducing interference between signal lines.
2Productivity
If the clock members and connection members are increased in number and complexity, then the charge transfer efficiency is improved, but heat generation in non-display area increases
Solution Approach 1:
Different clock members are assigned to different functional regions: first clock members connect to first gate lines for display area operation, while second clock members connect to second gate lines for non-display area operations. This local differentiation allows optimized charge transfer in each region while distributing heat generation across separate pathways, preventing concentration of thermal energy in a single location.
Solution Approach 2:
Linking members serve as intermediary structures that connect clock members to each other and to connection members. These intermediaries provide extended charge transfer pathways that reduce current density in individual conductors, thereby reducing resistive heating. The linking members act as thermal and electrical buffers that distribute energy load across a larger structural footprint.
3Productivity
If the clock line width is increased to improve charge transfer, then the charge transfer efficiency is improved, but the area occupied in non-display region increases
Solution Approach 1:
Clock members extend in multiple directions (first direction, second direction) and utilize vertical layering to achieve sufficient charge transfer capacity without increasing the planar width of individual lines. The three-dimensional arrangement allows current to distribute across multiple spatial pathways, effectively increasing transfer efficiency while maintaining compact footprint in the non-display region.
Solution Approach 2:
The clock line is segmented into multiple narrower clock members that collectively provide the charge transfer capacity of a single wide line. By distributing the current load across multiple segmented conductors arranged in different directions, the patent achieves equivalent or superior charge transfer efficiency while occupying less total area in the non-display region.
Data Source
AI summary
A display device includes a gate line, a gate driver, a clock-signal structure, and a connection structure. The gate driver is electrically connected to the gate line. The clock line may transmit a clock signal and includes a plurality of clock members and a first linking member. The first linking member electrically connects the plurality of clock members to each other and is angled relative to each of the plurality of clock members. The connection structure electrically connects the clock-signal structure and the gate driver and includes a plurality of connection members and a second linking member. The second linking member electrically connects the plurality of connection members to each other, is angled relative to each of the plurality of connection members, and crosses the first linking member.