Display Substrate Clock Line Sharing for Narrow Bezel Layout
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Solution Overview
Problem
The large number of clock signal lines in the peripheral area of display substrates necessitates a wider peripheral area, hindering the realization of a narrow frame design.
Innovation Solution
The implementation of a display substrate where multiple driving circuits share the same clock signal lines, reducing the total number of clock signal lines required and allowing for a narrower peripheral area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each driving circuit is provided with independent clock signal lines, then the reliability of signal transmission is improved, but the width of the peripheral area increases
Solution Approach 1:
Multiple driving circuits share common clock signal lines (first clock signal line and second clock signal line) instead of each having independent lines. The patent shows that driving circuits DC1 to DCn all connect to the same first clock signal line CK1 and second clock signal line CK2, reducing the total number of signal lines and narrowing the peripheral area width.
Solution Approach 2:
The clock signal lines are designed to serve multiple driving circuits simultaneously. The first clock signal line CK1 and second clock signal line CK2 function as universal signal lines that can provide clock signals to any or all of the driving circuits DC1 to DCn, increasing the versatility of the signal line system.
2Reliability
If the number of clock signal lines is increased to ensure proper operation of driving circuits, then the operational reliability is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple signal line functions into shared clock signal lines. Instead of having separate clock lines for each driving circuit, the system merges the clock signal distribution into common lines (CK1 and CK2) that serve multiple circuits, thereby reducing system complexity while maintaining operational reliability.
Solution Approach 2:
The signal line system is segmented into functional groups: clock signal lines (CK1, CK2), power signal lines (VGH, VGL), and data signal lines (DATA). This segmentation allows each type of signal to be managed independently through shared lines, reducing the overall complexity of the interconnection system.
Data Source
AI summary
A display substrate is provided to include: a base substrate including a display area and a peripheral area surrounding the display area; pixel units in array are in the display area; a driving module is in the peripheral area and is configured to provide electrical signals for the pixel units, to control the pixel units to operate; the driving module includes driving circuits each provided with a corresponding operating signal line group in the peripheral area; the signal line group includes at least two operating signal lines connected to the corresponding driving circuit, to provide electrical signals thereto; the at least two operating signal lines include first and second clock signal lines; the first clock signal lines for at least two driving circuits are a same first clock signal line; and/or the second clock signal lines for the at least two driving circuits are a same second clock signal line.