3D Image Display Clock Signal Frequency and Amplitude Control

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Solution Overview

Problem

Current 3D image display technologies face challenges in reducing heat and power consumption while maintaining high-speed processing for high-definition 3D image rendering.

Innovation Solution

A 3D image display system that includes a signal controller, a clock generator, and a gate driver, where the clock generator produces distinct clock signals for 2D and 3D image information, with the frequency and amplitude of these signals optimized to minimize power consumption and heat generation, and the gate driver integrates multiple stages connected to gate lines on a substrate for efficient voltage management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed processing is implemented for high-definition 3D image rendering, then processing speed is improved, but power consumption and heat generation increase

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The gate driver dynamically adjusts clock signal frequency and amplitude based on display mode. In 3D mode, it uses a first clock signal with higher frequency and amplitude for high-speed processing. In 2D mode, it switches to a second clock signal with lower frequency and amplitude to reduce power consumption. This dynamic adaptation resolves the contradiction between processing speed and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes operational parameters (clock frequency and amplitude) according to display requirements. The clock generator produces different clock signals with specific frequency and amplitude parameters optimized for different modes: high-frequency/high-amplitude for 3D, low-frequency/low-amplitude for 2D. This parameter optimization directly addresses the power-speed tradeoff.

Inventive Principle:
Principle #35Parameter changes

2Speed

If high amplitude clock signals are used for high-speed processing, then processing capability is improved, but heat generation increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidheat generation
Core Design Contradiction:
SpeedVSTemperature

Solution Approach 1:

The system dynamically adjusts clock signal amplitude based on operational mode. High amplitude is applied only when 3D high-definition rendering is required, while low amplitude is used during 2D display to minimize heat generation. This dynamic control prevents excessive heat buildup while maintaining processing capability when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The gate driver periodically switches between different clock signal configurations based on display mode requirements. This periodic adjustment of amplitude ensures that high processing power is delivered only when necessary, reducing overall heat generation while maintaining the ability to handle high-definition 3D rendering when required.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9092222B2Three dimensional image display
Publication Date: 2015.07.28 SAMSUNG DISPLAY CO LTD
  • US9092222B2 patent drawing
  • US9092222B2 patent drawing
  • US9092222B2 patent drawing

AI summary

A three-dimensional (“3D”) image display includes a signal controller which receives two-dimensional (“2D”) image information and 3D image information and generates control signals based on the 2D image information and the 3D image information, a clock generator which receives the control signals from the signal controller and generates a first clock signal corresponding to the 3D image information and a second clock signal corresponding to the 2D image information, and a gate driver which generates a gate-on voltage based on at least one of the first clock signal and the second clock signal, where a frequency of the second clock signal is lower than a frequency of the first clock signal and an amplitude of the second clock signal is less than an amplitude of the first clock signal.