Display Device Clock Synchronization During Vertical Blank
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Solution Overview
Problem
In display devices with adaptive refresh technology, the lack of signal transmission between the host processor and the driving controller during the vertical blank period leads to unsynchronized clock signals, resulting in inconsistent pulse intervals and unintended luminance changes perceived by the viewer.
Innovation Solution
A method where the driving controller adjusts the number of pulses in the second clock signal during the vertical blank period based on reference values set by comparing the number of pulses in the active period, ensuring synchronization and maintaining constant intervals between emission signal pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If adaptive refresh technology is applied to reduce power consumption, then energy efficiency is improved, but clock signal synchronization deteriorates due to no signal transmission during vertical blank period
Solution Approach 1:
The patent applies preliminary action by measuring the number of pulses in the first clock signal during the active period before the vertical blank period occurs, and using this measurement to determine the number of pulses in the second clock signal during the vertical blank period. This advance preparation ensures synchronization is maintained even when signal transmission stops during the vertical blank period, thus resolving the contradiction between power savings from adaptive refresh and clock signal synchronization.
2Adaptability or versatility
If the driving frequency of the display panel is changed, then adaptability is improved, but pulse interval consistency deteriorates due to unsynchronized clock signals
Solution Approach 1:
The patent implements feedback by measuring the actual number of pulses in the first clock signal during the active period, comparing it with the number of pulses in the second clock signal, and using this comparison to determine the appropriate number of pulses for the second clock signal during the vertical blank period. This feedback mechanism ensures that pulse intervals remain consistent even when the driving frequency changes, resolving the contradiction between adaptability and stability.
3Reliability
If the number of pulses in the second clock signal is adjusted during vertical blank period, then synchronization is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by enabling the driving controller to automatically measure the pulse numbers, calculate the appropriate pulse count for the vertical blank period, and adjust the second clock signal without requiring external intervention or complex control mechanisms. The system uses its own internal resources and measurements to maintain synchronization, thus improving reliability while minimizing the increase in device complexity.
Data Source
AI summary
A display device includes a driving controller, a display panel, and an emission driver. The driving controller generates a second clock signal having second pulses in response to a first clock signal having first pulses from an external device. The display panel includes pixels. The emission driver generates an emission signal having third pulses in response to the second clock signal and applies the emission signal to the pixels. The driving controller compares a number of the first pulses and a number of the second pulses, with a first reference value, and a second reference value, and sets a compensation value of the number of the second pulses, and the driving controller compensates for the second clock signal by adjusting the number of the second pulses existing in one horizontal time based on the compensation value in a vertical blank period of the frame period.