Display Data Driving Circuit for Fast Clock Training Feedback
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Solution Overview
Problem
As display panels with higher resolutions and increased pixel counts require faster data communication to process increased image data, existing technologies face challenges in speeding up data communication in display devices without compromising accuracy and reliability.
Innovation Solution
The implementation of a data driving device with low-speed and high-speed communication circuits, along with a lock control circuit, to perform clock training and adjust communication modes, utilizing a clock recovery circuit and equalizer for high-speed communication, and simplifying feedback mechanisms to improve data communication speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed communication mode is used to increase data communication speed, then productivity is improved, but reliability deteriorates due to potential misinterpretation of communication status
Solution Approach 1:
The patent performs low-speed clock training before high-speed communication to preliminarily establish synchronization. The lock control circuit generates a lock signal based on low-speed communication status first, then uses this as a foundation for high-speed clock training, ensuring reliable status detection before speed increase
Solution Approach 2:
The patent introduces a lock control circuit as an intermediary that manages the transition between low-speed and high-speed modes. This circuit generates lock signals that mediate the communication status feedback, preventing direct misinterpretation issues in high-speed mode by using the more reliable low-speed status as reference
2Measurement precision
If lock signal level changes frequently to reflect communication status, then measurement precision is improved, but device complexity increases due to multiple level management
Solution Approach 1:
The patent segments the communication process into distinct phases: low-speed clock training phase and high-speed clock training phase. Each phase has its own status signal generation rules, with the lock signal maintaining a first level during low-speed phase and allowing level changes only after transitioning to high-speed phase, simplifying control logic
Solution Approach 2:
The lock signal level management is made dynamic based on communication mode. The lock control circuit adjusts the lock signal level according to the current operation phase - maintaining stability during low-speed mode and enabling responsiveness during high-speed mode, optimizing both precision and simplicity
Data Source
AI summary
The present disclosure relates to a data processing device, a data driving device, and a system for driving a display device, and more particularly, to a data processing device, a data driving device, and a system for speeding up data communication in a display device.