Display Device Common Electrode Opening Reduces Gate Signal Delay
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Solution Overview
Problem
The integration of gate drivers in display panels leads to signal delay due to RC delay caused by signal lines, resulting in decreased charge time for pixels and deteriorated display quality.
Innovation Solution
A display device design that includes a display panel with a gate driver and a clock signal line group, where the common electrode has an opening overlapping the clock signal line group, with a width greater than the clock signal lines, and a light blocking member covering the opening, reducing the capacitance and load on the clock signals, thereby minimizing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If the gate driver is integrated on the display panel with clock signal lines, then the gate signals can be generated and transferred, but RC delay occurs causing gate signal delay and deteriorated display quality
Solution Approach 1:
The common electrode is extracted from the region overlapping with the clock signal line group by forming an opening in the common electrode. This removes the capacitive load from the clock signal lines, reducing RC delay and preventing gate signal delay while maintaining the integrated gate driver structure.
2Area of stationary object
If the common electrode completely covers the clock signal line group, then the display area is maximized, but the capacitance and load on clock signals increase causing signal delay
Solution Approach 1:
The common electrode is segmented by forming an opening in the region overlapping with the clock signal line group. This segmentation removes the capacitive load from specific clock signal lines while maintaining the common electrode's coverage over other display areas, thus improving signal transmission quality without significantly reducing the overall common electrode area.
3Reliability
If the opening width is increased to reduce capacitance, then the load on clock signals decreases, but the display area is reduced
Solution Approach 1:
The opening in the common electrode is strategically positioned only in the region overlapping with the clock signal line group, while the common electrode maintains full coverage in other display areas. This local modification reduces capacitance where it affects signal transmission without reducing the overall display area, thus resolving the contradiction between signal reliability and display area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces gate signal delay, enhances the reliability and operating margin of the gate driver, and improves the charge rate of pixels, suitable for large displays and high-resolution panels with narrow bezels.
Implementation Method 1
The delay of the gate signal may occur due to RC delay caused by signal lines such as, for example, a clock signal line through which a clock signal is transferred. The delay of the gate signal may cause the charge time of the pixel to decrease and cause crosstalk, thereby deteriorating the display quality.
Data Source
AI summary
A display device includes: a display panel including a display area in which a plurality of pixels are arranged and a non-display area around the display area. The display panel includes: a first substrate; a plurality of gate lines on the first substrate and configured to gate signals to a plurality of pixels; a gate driver on the first substrate, the gate driver including a plurality of stages configured to generate the gate signals to output them to the gate lines; a clock signal line group on the first substrate and including a plurality of clock signal lines configured to transmit clock signals to the stages; a second substrate facing the first substrate; and a common electrode on the second substrate, the common electrode having an opening overlapping the clock signal line group, and a width of the opening being greater than that of the clock signal line group.