Display Device Common Scanning Circuit Layout Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices with single channel thin film transistors require larger circuit areas due to the use of dynamic circuits based on capacitance, leading to increased space consumption and susceptibility to electrostatic discharge and coupling noise.
Innovation Solution
The configuration of a display device with a common scanning circuit and gate scanning circuit using single channel thin film transistors, where the shift register unit, connecting unit, and switch unit are disposed in a specific order on the array substrate to minimize interconnection length and reduce the number of crossing interconnections, thereby optimizing circuit layout and reducing electrostatic discharge and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a counter electrode selection circuit and scanning line drive circuit are configured of single channel transistors, then the circuit can be manufactured with simpler processes, but the circuit area is increased more than CMOS circuits
Solution Approach 1:
The patent combines the counter electrode selection circuit and scanning line drive circuit into a single integrated circuit block, sharing common transistors and interconnections. This merging reduces the total circuit area while maintaining the functionality of both circuits using single channel transistors.
Solution Approach 2:
The patent designs the circuit to use single channel transistors that perform multiple functions - serving as both switch elements and storage elements through their capacitance characteristics. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall circuit area.
2Device complexity
If dynamic circuits using capacitance are used in single channel transistor configurations, then the circuit can be implemented with fewer transistor types, but the circuit area is increased
Solution Approach 1:
The patent exploits the capacitance parameter of single channel transistors by designing the circuit to utilize the inherent capacitance of the transistor structure itself as the storage element. This parameter change approach allows the same transistor to serve dual purposes without requiring additional capacitance components that would increase area.
Solution Approach 2:
The circuit design allows the single channel transistors to serve themselves by using their own capacitance characteristics for data storage and switching functions. This self-service approach eliminates the need for separate dedicated capacitance elements, reducing overall circuit area.
3Adaptability or versatility
If circuit area is increased, then more functionality can be integrated, but susceptibility to electrostatic discharge and coupling noise increases
Solution Approach 1:
By merging the counter electrode selection circuit and scanning line drive circuit into a compact integrated structure, the patent reduces the overall area occupied while maintaining full functionality. This compact integration minimizes the exposure area to electrostatic discharge and reduces the length of interconnections that could act as antennas for coupling noise.
Solution Approach 2:
The patent introduces shielding structures and grounding interconnections as intermediary elements between functional circuit blocks. These intermediaries act as barriers against electrostatic discharge and coupling noise, protecting the circuit functionality without requiring increased area.
Data Source
AI summary
A display device includes a plurality of gate lines extended in a first direction, a plurality of common electrodes extended in the first direction, a gate scanning circuit that scans the plurality of the gate lines, and a common scanning circuit that scans the plurality of the common electrodes. The common scanning circuit includes a shift register unit, an interconnection connecting unit, and a switch unit. The gate scanning circuit and the common scanning circuit are configured of single channel thin film transistors. The gate scanning circuit is disposed between the shift register unit and the interconnection connecting unit, and the interconnection connecting unit is disposed between the gate scanning circuit and the switch unit in a planar view.