Flat Display Common Voltage Stabilization via Sync Timing
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Solution Overview
Problem
In liquid crystal displays, the variation in screen brightness due to the number of lines in an input video signal causes instability in image quality when common voltage is driven on AC, leading to inconsistent display performance.
Innovation Solution
A flat display device with a common voltage generation system that uses horizontal and vertical synchronization timing signals to generate specific frequency signals, performs multiplication and selection of these signals to stabilize the common voltage, ensuring it remains constant DC voltage regardless of the number of lines in a frame, thereby controlling the polarity of the common electrode effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If common voltage is driven on AC with polarity switching, then LC drive-ability is improved and image quality deteriorates from same polarity driving, but brightness variation occurs depending on the number of lines in a frame
Solution Approach 1:
The patent implements periodic polarity switching of the common voltage at two levels: (1) line-by-line reversal using a first signal with frequency fh/2, and (2) frame-by-frame reversal using a second signal with frequency fv/2. This dual-periodic action ensures that the average voltage stabilizes to constant DC voltage regardless of whether a frame contains an odd or even number of lines, thereby maintaining consistent screen brightness while preserving LC drive-ability improvements
Solution Approach 2:
The patent employs feedback mechanisms through selection control means that monitors the relationship between horizontal and vertical synchronization signals. The system detects whether one frame cycle contains an odd or even number of lines and automatically adjusts the common voltage control signal accordingly, selecting appropriate signal combinations to maintain stable average DC voltage and consistent brightness across different video signal configurations
2Extent of automation
If common voltage control signal is generated using horizontal and vertical synchronization signals, then polarity switching is achieved, but average voltage becomes unstable when frame contains even number of lines
Solution Approach 1:
The patent implements dynamic signal selection where the common voltage control signal is chosen based on real-time detection of frame line count parity. The selection control means dynamically switches between different signal combinations (third signal of positive polarity, third signal of negative polarity, or fourth signal from multiplication) depending on whether the frame contains an odd or even number of lines, ensuring stable average DC voltage under all operating conditions
Solution Approach 2:
The patent changes the parameters of the common voltage control signal based on the detected frame configuration. When odd number of lines are detected, one signal combination is selected; when even number of lines are detected, a different signal combination is selected. This parameter change approach ensures that the average voltage consistently stabilizes to DC voltage regardless of the specific frame structure
Data Source
AI summary
According to one embodiment of the present invention, a flat display device which makes drive voltage polarity of pixels of adjacent lines reversed polarity, while drives to reverse drive voltage polarity of the same line on a frame-by-frame basis, has common voltage generation circuit for supplying a common voltage signal to a facing electrode of the flat display device and a control circuit for generating a common voltage control signal supplied to the common voltage generation circuit. The control circuit obtains a control signal for generating common voltage whose average DC potential does not vary, by using a horizontal synchronization timing signal, a vertical synchronization timing signal, and a clock signal. In order to obtain the control signal, the device has an (fh/2) signal generation circuit, an (fv/2) signal generation circuit, an (fh×n) signal generation circuit, an multiplication circuit, a selection control circuit, and a selection circuit.