Display Controller Compression Mechanism for Bandwidth Reduction
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Solution Overview
Problem
Current display systems require high bandwidth and power consumption due to large on-chip and off-chip memory needs for de-interlacing and scaling, which complicates design and increases costs, especially in portable devices.
Innovation Solution
The method involves compressing image data using a procedure that separates MSB and LSB bits of DPCM coded pixels, with adaptive compression techniques such as VLC coding and truncation, to reduce storage density and bandwidth requirements, particularly focusing on the frame buffer and line image buffer within the display device controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large on-chip and off-chip memory is used for de-interlacing and scaling, then image quality is maintained, but power consumption increases and device complexity complicates
Solution Approach 1:
The patent applies DPCM (Differential Pulse Code Modulation) coding to change the parameter representation of image data from absolute pixel values to differential values. This transformation exploits the temporal and spatial redundancy in video sequences, where consecutive frames and adjacent pixels have similar values, enabling significant compression without losing image quality. The differential values require fewer bits to represent, reducing memory requirements and power consumption while maintaining visual fidelity.
Solution Approach 2:
The patent extracts and removes redundant information from image data by exploiting the correlation between consecutive frames and adjacent pixels. Through DPCM coding, the redundant absolute values are replaced with differential values that capture only the changes, effectively extracting and discarding the redundant information. This extraction process reduces the data volume stored in memory, thereby reducing power consumption and device complexity while preserving essential image quality information.
2Reliability
If large on-chip and off-chip memory is used for de-interlacing and scaling, then image quality is maintained, but device complexity increases
Solution Approach 1:
The patent transforms image data parameters from absolute pixel values to differential values through DPCM coding. This parameter change reduces the bit depth required to represent image data, allowing the same image quality to be achieved with smaller memory structures. The simplified data representation reduces the complexity of memory management, data transfer, and processing logic in the display system.
Solution Approach 2:
The patent segments the image data processing into distinct stages: DPCM encoding, VLC (Variable Length Coding), and selective truncation. This segmentation allows each processing stage to be optimized independently and applied selectively based on the specific requirements of different image regions and content types, reducing overall system complexity compared to applying a single complex memory system throughout.
3Productivity
If high bandwidth memory interface is used, then de-interlacing performance is improved, but power consumption increases
Solution Approach 1:
The patent changes the data representation parameters from full-resolution absolute pixel values to compressed differential values. This parameter transformation reduces the data width and volume that must be transferred through the memory interface, allowing de-interlacing operations to be performed with lower bandwidth requirements. The compressed data format maintains sufficient information for quality de-interlacing while reducing the power consumption of the memory interface by a significant margin.
4Speed
If on-chip cache is increased, then processing speed is improved, but chip area increases
Solution Approach 1:
The patent applies DPCM coding to change the parameter representation of image data, which reduces the number of bits required to represent each pixel. This parameter compression allows the same processing speed to be achieved with a smaller cache size, or alternatively, provides faster processing for the same cache size. The reduced data width directly translates to smaller cache memory requirements while maintaining processing throughput.
Solution Approach 2:
The patent creates a compressed representation (copy) of the image data in the on-chip cache using DPCM-encoded differential values instead of storing full absolute pixel values. This compressed copy requires less space in the cache memory while containing sufficient information for rapid processing operations, thereby improving processing speed without proportionally increasing chip area.
Data Source
AI summary
A codec device is disposed in a display control device for instantly supplying decompressed image data to manipulating devices in the display control chip. Reference images are stored in compressed format after instantly compressed by the codec device. In addition, MSB portions and LSB portions are separately compressed for gaining higher compression ratio. Predication of the pixel value is also modified in variable length coding. On-chip line buffer is also applied with the instant compression mechanism. Fixed compression ratio is predetermined to actually downsize the chip design for the worst case.