Display Device Circuit With Conductive Pattern for Kickback Control

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Solution Overview

Problem

Existing organic light-emitting display devices face issues with excessive reduction of transistor gate electrode voltage due to kickback, which can be exacerbated by replacing some PMOS transistors with NMOS transistors, leading to altered kickback voltage characteristics.

Innovation Solution

The display device incorporates a conductive pattern that overlaps and is insulated from scan lines, featuring a stem part and branch parts, along with parasitic capacitors to manage voltage, and includes PMOS and NMOS transistors to stabilize gate electrode voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If NMOS transistors are used to replace PMOS transistors, then device performance is improved, but kickback voltage characteristics deteriorate causing excessive gate electrode voltage reduction

Engineering Contradiction:
Improvedevice performanceVSAvoidgate electrode voltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a conductive pattern as an intermediary element between the scan lines and the gate electrode. This conductive pattern includes a stem part extending in one direction and a branch part branching from the stem part and overlapping the first scan line, creating parasitic capacitance that acts as a buffer to mitigate the harmful kickback voltage effects while preserving the performance benefits of NMOS transistors.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conductive pattern with stem part and branch part is added, then gate electrode voltage stability is improved, but device complexity increases

Engineering Contradiction:
Improvegate electrode voltage stabilityVSAvoidconductive pattern structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive pattern serves multiple functions simultaneously: it acts as an electrode for creating parasitic capacitance, provides structural support, and facilitates electrical connections. The stem part and branch part configuration allows a single conductive pattern element to perform voltage stabilization across multiple gate electrodes, reducing the need for separate components and thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents excessive voltage reduction at the transistor gate electrode, ensuring stable operation and reduced leakage of driving current, thereby enhancing display performance.

Implementation Method 1

a first parasitic capacitor formed between the gate electrode of the second transistor and the gate electrode of the first transistor; and a second parasitic capacitor formed between the gate electrode of the third transistor and the gate electrode of the first transistor

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS12431081B2Display device
Publication Date: 2025.09.30 SAMSUNG DISPLAY CO LTD
  • US12431081B2 patent drawing
  • US12431081B2 patent drawing
  • US12431081B2 patent drawing

AI summary

A display device including a light-emitting diode, a first transistor, a second transistor, a data line connected to the second transistor and configured to transmit a data signal, a third transistor, a first signal line connected to a gate electrode of the second transistor and configured to transmit a first signal, a second signal line connected to a gate electrode of the third transistor and configured to transmit a second signal, and a connect portion connected to a gate electrode of the first transistor and an electrode of the third transistor, in which the connect portion overlaps the first signal line and the second signal line, and an overlapping area between the connect portion and the first signal line is different from an overlapping area between the connect portion and the second signal line.