Display Control Circuit Clock Frequency Adjustment for Buffer Reduction
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Solution Overview
Problem
The eDP/DP interface lacks vertical synchronization, leading to irregular video data transmission, which requires large line or frame buffers in OLED panels to maintain emission duty cycle, increasing circuit costs and complexity.
Innovation Solution
A control circuit that determines the presence of input video data at a predetermined time to output video data and clock signals with specific frequencies, switching to a higher clock frequency when data is not received, allowing for reduced buffer size and maintaining emission duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large line buffers or frame buffers are deployed to queue video data for OLED panel, then the emission duty can be maintained correctly, but the circuit area and costs increase significantly
Solution Approach 1:
The patent changes the clock frequency parameter dynamically - using a first clock frequency when video data arrives at predetermined times, and a second (higher) clock frequency when data arrival is delayed. This frequency adjustment allows the system to maintain emission duty cycle accuracy without requiring large buffers to queue data
Solution Approach 2:
The system transitions from a static buffer-based approach to a dynamic clock frequency adjustment approach. The control circuit dynamically changes operating parameters (clock frequency) based on real-time data arrival conditions, eliminating the need for large static buffer memory structures
2Stability of the object's composition
If the display driver circuit delays video data to refresh the panel at predetermined times, then synchronization is improved, but the complexity of data handling increases
Solution Approach 1:
The control circuit monitors whether video data arrives at predetermined times and uses this feedback to adjust the clock frequency. When data arrives on time, the first clock frequency is used; when delayed, the second higher frequency is applied. This feedback mechanism automates synchronization without complex manual data handling
Solution Approach 2:
The system prepares by detecting data arrival timing in advance and proactively adjusts the clock frequency before processing video data. This preliminary detection and adjustment simplifies subsequent data handling by pre-synchronizing the system state
Data Source
AI summary
A method used for a control circuit for controlling a display panel includes steps of: determining whether there is an input video data received at a predetermined time; outputting an output video data and a clock signal having a first frequency to the display panel when determining that there is an input video data received at the predetermined time; and stopping outputting the output video data but outputting the clock signal having a second frequency to the display panel when determining that there is no input video data received at the predetermined time. Wherein, the second frequency is higher than the first frequency.