Display Control Device Halt Period for Interlace Driving Power Reduction
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Solution Overview
Problem
Interlace driving techniques for display panels tend to increase power consumption, especially in high-definition systems, necessitating a reduction in power consumption without increasing image data transmission rates or bandwidth.
Innovation Solution
The implementation of an interval interlace mode where a halt period is inserted between odd-numbered and even-numbered field drive periods, along with the reduction of source line switchings by controlling the supply of power voltage to the source driver and deactivating gate line control signals during these periods, and enabling output synchronization signals to persist across adjacent display periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interlace driving is used to increase the number of image drawing operations without increasing transmission data amount, then the image refresh rate is improved, but the power consumption increases
Solution Approach 1:
The patent implements a halt period between odd-numbered and even-numbered field drive periods in interlace driving mode. This periodic interruption allows the source driver to stop switching source line selection signals and the gate line control signals to be deactivated during the halt period, thereby reducing power consumption while maintaining the interlace driving capability for high refresh rates
Solution Approach 2:
The output synchronization signals are enabled to persist across adjacent display periods including the halt period. This preliminary action of maintaining signal state prevents the need for repeated signal transitions at the boundaries of display periods and halt periods, further reducing the number of switchings and power consumption
2Use of energy by moving object
If the number of source line switchings is reduced during halt period, then the power consumption is reduced, but the switching control complexity increases
Solution Approach 1:
The patent merges the control of source line switches and gate line control signals under a unified halt period management mechanism. The source driver stops switching source line selection signals during the halt period, and the gate line control signals are deactivated simultaneously, simplifying the overall control logic by coordinating these operations rather than managing them independently
Data Source
AI summary
A halt period is inserted between a drive period in an odd-numbered field and a drive period in an even-numbered field in interlace driving. When drive signals driving subpixels are time-divisionally supplied to the display panel in units of subpixel types, switch control signals controlling source line switches which distribute the drive signals associated with respective subpixels to the corresponding source lines are generated so that the number of switching of the source line switches are reduced.