Display Control IC Video Output Generator Reset Timing
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Solution Overview
Problem
Existing display devices face issues with random phase relationships between internal synchronization signals and external synchronization signals, leading to operational failures and potential side effects when attempting to solve these problems.
Innovation Solution
A display control integrated circuit that includes a video output generator and a display output control circuit, which generates a set of display control signals to synchronize the timing of the input vertical synchronization signal with the display vertical synchronization signal, achieving frame lock within two frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the main control chip generates an internal synchronization signal to complete internal operations, then the internal operations can be performed, but the phase relationship between the internal synchronization signal and external synchronization signals becomes random, causing operational failures
Solution Approach 1:
The patent applies preliminary action by performing a reset operation on the video output generator at a predetermined time point within the vertical synchronization signal interval, before the next frame processing begins. This preliminary reset ensures that the internal synchronization signal is realigned with the external display vertical synchronization signal at the start of each frame, preventing phase drift and ensuring reliable operation without affecting the normal processing flow.
2Reliability
If conventional methods are used to solve the phase relationship problem, then some synchronization issues may be addressed, but additional problems and side effects are introduced
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the reset timing parameter within the vertical synchronization signal interval. By setting the reset to occur at a specific time point that corresponds to a predetermined timing ratio of the interval, the patent achieves reliable synchronization while avoiding the side effects associated with other timing approaches. This precise parameter control ensures that the reset operation occurs at the optimal moment to align phases without disrupting other display operations.
3Reliability
If the timing alignment between internal and external synchronization signals is not achieved quickly, then frame lock cannot be established promptly, but the display panel may enter protection mode and stop displaying
Solution Approach 1:
The patent applies periodic action by implementing a reset operation that occurs periodically at the beginning of each vertical synchronization signal interval. This periodic reset ensures that the internal synchronization is continuously realigned with the external display synchronization signal, achieving frame lock within two frames as specified. The periodic nature of this action prevents timing drift accumulation and ensures rapid establishment of frame lock, thereby maintaining display continuity without prolonged delays.
Data Source
AI summary
A display control integrated circuit (IC) applicable to performing video output (VO) generator reset control in a display device includes multiple sub-circuits such as a VO generator and a display output control circuit. The VO generator generates an input vertical synchronization (IVS) signal for controlling playback of video data. The display output control circuit performs display output control, and more particularly, generates a set of display control signals to control a display output module within the display device to perform display operations. The set of display control signals may include a display vertical synchronization (DVS) signal for being used as timing reference of a timing controller within the display output module. During a time interval between time points when two consecutive pulses carried by the DVS signal appear, the display output control circuit sends a reset signal to the VO generator at an intermediate time point to reset it.