Display Control Device Parallel Line Buffer Memory Management
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Solution Overview
Problem
High-resolution display in portable communication terminals faces challenges due to increased memory operation latency for write and read operations in frame buffer memory, especially when dealing with high-definition images, and existing compression techniques complicate arbitration logic and limit memory operation speed.
Innovation Solution
A display control device with multiple line buffers allows parallel writing and reading of display data, compressing metadata read from line buffers, and decompressing data stored in the frame buffer memory to drive signal electrodes in synchronization with display timing, enhancing timing margins and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If display data is compressed and stored in frame buffer memory, then memory operation speed is improved, but processing time for compression is limited and system complexity increases
Solution Approach 1:
The patent divides the frame buffer memory into multiple line buffers (first line buffer, second line buffer, third line buffer, fourth line buffer) that can operate independently and in parallel. This segmentation allows simultaneous compression and reading operations without contention, improving memory operation speed while keeping each buffer's control logic simple.
Solution Approach 2:
The patent performs compression of display data before storing it in the line buffers. By compressing the data in advance (preliminary action), the actual memory read operations can proceed at full speed without real-time compression delays, improving overall memory operation speed.
2Loss of time
If multiple line buffers are used for parallel write and read operations, then timing margins are enhanced and latency is reduced, but device complexity increases
Solution Approach 1:
The patent uses four separate line buffers (first, second, third, and fourth line buffers) that can be written to and read from in parallel. This segmentation eliminates contention between write and read operations, reducing memory access latency and enhancing timing margins for high-resolution display.
Solution Approach 2:
The patent implements a periodic switching mechanism where the buffer selection is controlled in cycles (e.g., switching between first/second buffers and third/fourth buffers). This periodic action simplifies the control logic compared to arbitrary buffer management, reducing complexity while maintaining parallel operation benefits.
3Quantity of substance
If display data is compressed to fit memory, then memory usage efficiency is improved, but image quality may be degraded
Solution Approach 1:
The patent applies compression selectively to metadata portions of the display data while maintaining full precision for the actual image data. This partial compression approach improves memory usage efficiency for control information while preserving complete image quality for display purposes.
Data Source
AI summary
Provided is a display control device capable of coping with high-resolution display readily in terms of conducting data write and read on a frame buffer memory in time for the timing of display. The display control device has a plurality of line buffers, and is arranged so that a writing process for writing, into part of the line buffers, display lines of display data from outside, and a reading process for reading out written display lines of display data from other line buffers can be conducted in parallel. In the display control device, display-line data read out from the line buffers are compressed and stored in the frame buffer memory. The compression-display data read out from the frame buffer memory are read out for each line, and decompressed into display lines of display data. The decompressed display data are used to drive signal electrodes of a display device.