Display Controller Memory Burst Mode Compression
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Solution Overview
Problem
Liquid crystal display (LCD) devices face issues with response speed, particularly when displaying moving images, due to the low response speed of liquid crystals, leading to afterimages, and require high-capacity, high-speed external memory for efficient frame data processing, which is costly.
Innovation Solution
A display controller with a timing controller that compresses frame data, generates FIFO input data, writes and reads data in burst mode to external memory, and decodes data to output previous frame data, utilizing dual-port memories for efficient data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-capacity, high-speed external memory is used for frame data processing, then data processing efficiency is improved, but cost increases
Solution Approach 1:
The memory system is segmented into two parts: a small internal memory buffer for temporary storage and a large external memory for frame data storage. The controller divides the memory hierarchy into fast internal memory for buffering and cost-effective external memory for bulk storage, resolving the contradiction between speed and cost.
Solution Approach 2:
The memory controller acts as an intermediary between the fast internal memory and the slower external memory. It manages data transfer between these two memory types, optimizing the balance between access speed and storage capacity, allowing the system to use cheaper external memory while maintaining performance through intelligent data handling.
2Quantity of substance
If frame data is compressed and written to external memory, then memory capacity requirement is reduced, but write/read operation time increases
Solution Approach 1:
The system performs preliminary compression of frame data before writing to external memory, reducing the amount of data that needs to be stored. This pre-processing action decreases the memory capacity requirement while the controller manages the timing of read operations to minimize overall time loss.
Solution Approach 2:
The memory controller continuously manages data transfer between internal and external memory, maintaining continuous useful action. It overlaps compression, writing, and reading operations where possible, ensuring that the system maintains high throughput despite the sequential nature of memory operations.
3Speed
If burst mode reading/writing is implemented, then data transfer speed is improved, but memory controller complexity increases
Solution Approach 1:
The memory controller merges multiple memory operations into burst mode transfers, combining multiple read/write cycles into a single optimized operation. This consolidation increases data transfer speed by reducing the overhead of individual memory transactions while managing complexity through integrated control.
Solution Approach 2:
The memory controller is designed with multi-functional capabilities that can handle both compression/decompression operations and burst mode data transfer. This universal design consolidates multiple functions into a single controller unit, managing complexity through functional integration rather than separate dedicated circuits.
Data Source
AI summary
A display controller is provided. The display controller includes an external memory and a timing controller which compresses current frame data to generate front first in-first out (FIFO) input data, temporarily stores the front FIFO input data and writes the front FIFO input data to the external memory in a burst mode, and reads data from the external memory in the burst mode, temporarily stores the read data as back FIFO output data, and decodes the back FIFO output data to output previous frame data.