Display Controller Clock Modulation for EMI Reduction
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Solution Overview
Problem
Display controllers face challenges in reducing electromagnetic interference (EMI) emissions and preventing data buffer under-runs due to high-frequency clock signals, especially in high-resolution display panels, which can lead to visual artifacts.
Innovation Solution
A display controller that modulates the reference clock signal based on the amount of pixel data being fetched from memory, using a clock divider and look-up table to adjust the frequency within a specific spectrum, thereby reducing EMI and preventing data buffer under-runs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the reference clock signal is increased to transfer larger blended pixel data for high-resolution display panels, then the transfer rate of pixel data is improved, but the electromagnetic interference (EMI) emissions increase and exceed regulatory limits
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The system dynamically varies the clock frequency within a specified range based on data transfer requirements, allowing optimization between transfer rate and EMI emissions. The frequency can be adjusted in real-time to match the actual data transfer needs of different display resolutions and graphic data layer configurations.
Solution Approach 2:
The patent implements parameter changes by modifying the frequency parameter of the reference clock signal. By changing the frequency parameter within a defined range, the system achieves different transfer rates while maintaining EMI compliance. This allows flexible adaptation to various display panel resolutions and data transfer demands without being constrained by a fixed frequency.
2Object-generated harmful factors
If the frequency of the reference clock signal is modulated to reduce EMI emissions, then electromagnetic interference is reduced, but the data transfer rate decreases which may cause buffer under-runs
Solution Approach 1:
The system dynamically adjusts the clock frequency based on actual data transfer requirements. When the number of graphic data layers is small and transfer demands are low, the frequency is reduced to minimize EMI. When data transfer requirements increase, the frequency is raised to prevent buffer under-runs, achieving adaptive optimization of both EMI and transfer performance.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors the number of graphic data layers and data transfer requirements, then adjusts the clock frequency accordingly. This closed-loop control ensures that the frequency is optimized for current conditions, preventing both EMI excess and buffer under-runs by responding to actual system state.
3Device complexity
If a fixed frequency reference clock signal is used, then the system operation is simplified, but the electromagnetic interference emissions concentrate in a narrow spike with large amplitude exceeding EMI limits
Solution Approach 1:
The patent transitions from a static fixed-frequency system to a dynamic variable-frequency system. While this increases operational complexity, it resolves the EMI issue by spreading spectral energy across a wider range. The added complexity is justified by the ability to comply with EMI regulations while maintaining effective data transfer.
Solution Approach 2:
The system changes the frequency parameter of the reference clock signal from a fixed value to a variable range. This parameter change transforms the EMI profile from a concentrated spike to a distributed spectrum, achieving compliance with regulatory limits while preserving system functionality.
4Object-generated harmful factors
If the clock dividing ratio is varied to modulate the reference clock signal frequency, then the spectral energy is spread reducing EMI amplitude, but the maximum frequency range is limited by the tolerance limit of the reference clock signal
Solution Approach 1:
The patent utilizes parameter changes within the available frequency tolerance range to achieve EMI reduction. By carefully selecting and adjusting the clock dividing ratio, the system maximizes the usable frequency modulation range while staying within the reference clock signal's tolerance limits, thereby optimizing both EMI performance and adaptability.
Data Source
AI summary
A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.