Display Controller Constant Dot Clock Refresh Rate Switching

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Solution Overview

Problem

Existing display systems face issues with noise and screen rearrangement when switching between high and low refresh rates, leading to unnatural user experiences and increased power consumption due to sudden changes in dot clock frequency and horizontal synchronization signal cycles.

Innovation Solution

A display controller that generates a constant dot clock frequency and horizontal synchronization signal cycle, independent of refresh rate changes, to prevent noise and ensure uniform pixel charging, thereby maintaining image quality and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the refresh rate is decreased to reduce power consumption, then power consumption is reduced, but the image quality and responsiveness deteriorate

Engineering Contradiction:
Improvepower consumptionVSAvoidimage quality
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The system dynamically switches between two refresh rates (60 Hz and 40 Hz) based on the display state. High refresh rate (60 Hz) is used during active display states to maintain image quality, while low refresh rate (40 Hz) is used during standby states to reduce power consumption. This dynamic adaptation resolves the contradiction between power consumption and image quality.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If the refresh rate is switched between high and low modes, then power consumption can be optimized, but noise and screen disarrangement occur

Engineering Contradiction:
Improvepower consumptionVSAvoidnoise and screen disarrangement
Core Design Contradiction:
Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

Before switching the refresh rate, the system performs preliminary actions: setting the dot clock frequency to a predetermined value and adjusting the horizontal synchronization signal cycle to a predetermined value. These preliminary adjustments prevent noise and screen disarrangement that would otherwise occur during refresh rate switching, while still allowing power consumption optimization through refresh rate changes.

Inventive Principle:
Principle #10Preliminary action

3Speed

If the dot clock frequency is changed with refresh rate, then the refresh rate can be adjusted, but noise occurs and screen becomes disarranged

Engineering Contradiction:
Improverefresh rateVSAvoidnoise and screen disarrangement
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The invention extracts the dot clock frequency control from the refresh rate switching mechanism. While the refresh rate changes between 60 Hz and 40 Hz, the dot clock frequency is maintained at a predetermined constant value. This separation of controls prevents noise and screen disarrangement that would result from changing the dot clock frequency during refresh rate transitions.

Inventive Principle:
Principle #2Taking out (Extraction)

4Speed

If the horizontal synchronization signal cycle is changed with refresh rate, then the refresh rate can be adjusted, but pixel charging becomes non-uniform and image quality deteriorates

Engineering Contradiction:
Improverefresh rateVSAvoidpixel charging uniformity
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The invention extracts the horizontal synchronization signal cycle control from the refresh rate switching mechanism. While the refresh rate changes between 60 Hz and 40 Hz, the horizontal synchronization signal cycle is maintained at a predetermined constant value. This ensures uniform pixel charging and prevents image quality deterioration, while still allowing refresh rate adjustment for power optimization.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8947419B2Display controller, display device, display system, and method for controlling display device
Publication Date: 2015.02.03 SHARP KK
  • US8947419B2 patent drawing
  • US8947419B2 patent drawing
  • US8947419B2 patent drawing

AI summary

In one embodiment of the present application, a display controller is capable of changing a refresh rate, indicative of how often a screen displayed on a display device having a plurality of pixels is switched, between a low refresh rate of 40 Hz and a normal refresh rate of 60 Hz and generates (i) a dot clock (reference clock) serving as a timing signal indicative of a timing of operation in the display device, (ii) video data indicative of an image to be displayed on the screen, (iii) Hsync for defining a horizontal period of a display on the screen, and (vi) Vsync for defining a vertical period of the display on the screen, so as to supply the dot clock, the video data, Hsync, and Vsync to the display device, wherein the display controller includes a dot clock generation circuit for generating the reference clock whose frequency is constant without depending on a change of the refresh rate. This makes it possible to provide the display controller which can suppress occurrence of noise also in switching the refresh rate and which does not allow any screen derangement which is caused by the noise.