Display Controller Driver Test Pattern Bypass

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Solution Overview

Problem

Conventional controller drivers for display panels face inefficiencies in test operation modes due to shared transmission channels, leading to increased testing time and reduced efficiency, particularly evident in devices like mobile phones where SRAM access speeds impact waiting times during data testing.

Innovation Solution

Incorporating a data selection unit between the memory control circuit and the data line driving circuit, which allows for direct transmission or generation of test patterns without writing to or reading from the image data memory, enabling selective output to channels and reducing the need for frequent memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If test patterns are transmitted through the image data memory using the same transmission channel as display data, then the existing memory structure can be utilized, but the testing time increases and test efficiency decreases

Engineering Contradiction:
Improvetest efficiencyVSAvoidtesting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the transmission path by introducing a dedicated test pattern transmission channel that operates independently from the image data memory. The test pattern transmission unit provides a separate route for test data, allowing simultaneous or independent testing without interfering with normal display operations, thus resolving the bottleneck caused by shared channel usage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The test pattern transmission unit acts as an intermediary component between the external test equipment and the data line driving circuit. This intermediary provides a dedicated pathway for test patterns, eliminating the need to use the image data memory for test data storage and transmission, thereby reducing testing time and improving test efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the controller driver uses a conventional architecture with shared transmission channels, then device complexity is reduced, but test operation speed is limited by SRAM access speeds

Engineering Contradiction:
Improvetest operation speedVSAvoidcontroller driver architecture
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by providing test patterns directly through the test pattern transmission unit before they would otherwise need to be loaded into the image data memory. This preliminary transmission path eliminates the need for SRAM access during testing, thereby increasing test operation speed without significantly increasing device complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller driver architecture is enhanced with multi-functionality by incorporating the test pattern transmission unit that serves both testing operations and maintains compatibility with existing display data transmission. This universal design allows the same controller driver to handle both normal display operations and accelerated testing operations without requiring complete architectural redesign.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8842105B2Controller driver for driving display panel
Publication Date: 2014.09.23 NOVATEK MICROELECTRONICS CORP
  • US8842105B2 patent drawing
  • US8842105B2 patent drawing
  • US8842105B2 patent drawing

AI summary

A controller driver for driving a display panel is provided. The controller driver comprises a timing control circuit, a data memory unit, a data selection unit and a data line driver circuit. The data memory unit stores image data. The data selection unit coupled to the data memory unit outputs the image data provided from the data memory unit as a display data, or generates the display data in accordance with a command or test patterns provided from an external processor. The data line driver circuit is coupled to the timing control circuit and the data selection unit. The data line driver circuit receives the display data from the data selection unit, and outputs corresponding grayscale voltages according to the control signal outputted from the timing control circuit.