Display Controller Dynamic Sleep State Power Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display technologies face inefficiencies in achieving the deepest power-saving states (PKG C10) due to dependencies on display engines for time synchronization, leading to higher CPU/SoC power consumption during tasks like web browsing and video playback.
Innovation Solution
Implementing a dynamic sleep state mechanism that offloads phase-locked loop and timer logic to a separate low-power rail, allowing the CPU/SoC to enter the deepest power-saving state (PKG C10) by maintaining time synchronization through an always-on power domain, and enabling deep sleep in both long and short loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display controller maintains time synchronization with the display panel using traditional timing logic, then time synchronization is maintained, but the CPU/SoC cannot enter the deepest power-saving state (PKG C10)
Solution Approach 1:
The patent segments the time synchronization function from the main display controller by implementing it in a separate always-on power domain. This allows the main controller to enter deep sleep state (PKG C10) while the segmented timing logic in the always-on domain continues to maintain time synchronization with the display panel.
Solution Approach 2:
The patent introduces an intermediary always-on power domain that acts as a mediator between the CPU/SoC and the display panel. This intermediary maintains time synchronization using phase-locked loop and timer logic, allowing the CPU/SoC to enter deep power-saving states without losing synchronization.
2Use of energy by moving object
If the display controller enters deep sleep state to save power, then power consumption is reduced, but time synchronization with the display panel is lost
Solution Approach 1:
The patent segments the power domains into main and always-on sections. The main domain can enter deep sleep to reduce power consumption, while the segmented always-on domain maintains time synchronization functionality, resolving the contradiction between power saving and synchronization reliability.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the always-on power domain with timing logic before the CPU/SoC enters sleep state. This ensures time synchronization is already established and maintained independently, allowing the main controller to sleep without losing synchronization.
3Reliability
If the phase-locked loop and timer logic remain active in the display controller, then time synchronization is maintained, but the CPU/SoC cannot achieve the deepest power-saving state
Solution Approach 1:
The patent extracts the phase-locked loop and timer logic from the main display controller and places them in a separate always-on power domain. This extraction allows the main controller to power down completely to achieve PKG C10 state while the extracted timing logic continues to operate independently to maintain synchronization.
Solution Approach 2:
The always-on power domain with its phase-locked loop and timer logic serves as an intermediary that maintains time synchronization without requiring the main CPU/SoC or display controller to remain active, enabling deepest power-saving states.
Data Source
AI summary
Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.