Display Controller Indirect Addressing via Extra Pin
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Solution Overview
Problem
Existing indirect addressing schemes for display controllers require multiple bus cycles to access memory, leading to decreased throughput, especially when accessing non-consecutive memory locations, as they necessitate index and data cycles for each access.
Innovation Solution
The introduction of an extra pin configured to operate in either active low memory chip select or register/memory strobe mode reduces the number of bus cycles required for memory access by allowing direct selection of memory without accessing a register block, thereby enabling performance similar to register accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If indirect addressing mode is used to reduce pin count, then device complexity is reduced, but productivity decreases due to multiple bus cycles required for memory access
Solution Approach 1:
The patent applies dynamics by making the third pin's function changeable between address mode and data mode through signal toggling. This dynamic reconfiguration allows the same pin to serve different purposes during the access cycle, reducing the number of pins needed while maintaining efficient memory access throughput.
2Adaptability or versatility
If traditional indirect addressing is used to access non-consecutive memory locations, then addressing flexibility is improved, but productivity decreases due to requiring 12 cycles per memory access
Solution Approach 1:
The patent applies preliminary action by using the third pin to pre-indicate whether address information or data will be transmitted before the actual transfer occurs. This advance signaling allows the system to prepare for the upcoming operation, enabling faster processing of non-consecutive memory accesses while maintaining addressing flexibility.
3Ease of operation
If register access protocol is used for memory access, then ease of operation is improved, but device complexity increases due to requiring memory address registers and memory data registers
Solution Approach 1:
The patent applies universality by making the third pin multi-functional, serving as both an address/data indicator and a mode selector. This single pin performs multiple functions that would otherwise require separate dedicated pins or registers, simplifying the overall device structure while maintaining ease of memory access operation.
Data Source
AI summary
A display controller is provided. The display controller is configured to provide an indirect addressing mode to access a memory location within the display controller. The display controller includes a first pin configured to enable access to one of a register of the display controller or a memory region of the display controller based upon a logical level of a first signal received by the first pin. A second pin is included. The second pin is configured to define the access to the register or the memory region as one of address information or data based upon a logical level of a second signal received by the second pin. The display controller includes an extra pin mode module configured to enable the first signal to select the data to access memory without accessing a register block. A device and methods for implementing an indirect addressing mode is also provided.