Display Controller Memory Request Aggregation
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Solution Overview
Problem
The increasing power and complexity of computer systems lead to bottlenecks in memory subsystems due to continuous memory access by display pipelines, preventing the memory subsystem from entering a low-power mode and resulting in high power consumption.
Innovation Solution
A display controller is configured to process image data and aggregate memory requests for each pixel-processing pipeline, waiting until a programmable number of pixels are left in the line buffer before issuing read requests, allowing the memory controller to transition to a low-power mode when no requests are received.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If display pipelines continuously access memory for frame data, then image processing and display functionality is maintained, but the memory subsystem cannot enter low-power mode resulting in high power consumption
Solution Approach 1:
The system pre-loads frame buffer data into the line buffer before the display pipeline needs it. By anticipating the next frame's data requirements and fetching it in advance when the line buffer has space, the system avoids continuous memory access during critical display periods, enabling the memory subsystem to enter low-power modes while maintaining display functionality.
Solution Approach 2:
The line buffer acts as an intermediate storage that continuously holds frame data available to the display pipeline without requiring continuous memory access. This decouples the display pipeline's continuous operation from the memory subsystem's continuous activity, allowing the memory to remain static or enter low-power modes while the line buffer supplies data on-demand to the display pipeline.
2Productivity
If multiple memory requests are issued continuously by display pipelines, then data availability for processing is maintained, but the memory subsystem performance is reduced due to bottleneck and repeated overhead processing
Solution Approach 1:
Multiple scattered memory requests from different display pipelines are merged into fewer, more efficient batch requests. The line buffer accumulates data from multiple sources and presents it as a single coherent frame buffer read operation, reducing the total number of memory transactions and eliminating repeated overhead processing while maintaining data availability for all pipelines.
Solution Approach 2:
The line buffer serves as an intermediary between the memory subsystem and multiple display pipelines. Instead of each pipeline directly accessing memory individually (creating multiple requests and overhead), the line buffer mediates by receiving data once and distributing it to multiple pipelines as needed, thereby reducing memory subsystem complexity and improving performance.
3Ease of operation
If the memory subsystem remains active to satisfy continuous display pipeline access, then data can be retrieved when needed, but power consumption increases significantly
Solution Approach 1:
The system performs preliminary data retrieval by loading frame buffer contents into the line buffer in advance, during periods when the display pipeline is not actively consuming data. This allows the memory subsystem to be inactive (and thus low-power) during critical display periods while still providing rapid data access when the pipeline needs it, as the data is already cached in the line buffer.
Solution Approach 2:
The line buffer enables the display pipeline to serve its own data needs without continuous memory subsystem support. By maintaining a local copy of frame data in the line buffer, the pipeline can operate autonomously during display cycles, retrieving data from the buffer rather than continuously requesting it from memory, thereby reducing overall power consumption while maintaining ease of operation.
Data Source
AI summary
A system and method for efficiently scheduling memory access requests from a display controller pipeline. The display controller monitors the amount of data in the line buffers in the internal pixel-processing pipelines. The display controller waits until the amount of data in a given line buffer has fallen below an amount equal to the pixel width of the region being rendered by the internal pixel-processing pipeline before issuing memory requests to the memory controller. When the memory controller is not processing received memory requests, the memory controller transitions to a low-power state.