Display Controller Modulated Clock for Luminance Uniformity
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Solution Overview
Problem
In high-resolution display apparatuses with large screens, such as 4K or 8K panels, the increasing load capacitance of data lines and shorter driving periods lead to luminance unevenness due to signal waveform distortions, causing inadequate voltage levels to be reached in pixel electrodes, resulting in deteriorated image quality.
Innovation Solution
A display apparatus and controller that utilize a modulated clock signal with a frequency changing at a predetermined rate in one frame period, synchronizing the provision of scanning pulse signals and gradation voltage signals to ensure consistent voltage writing across the display panel, thereby adjusting the selection and data periods to compensate for impedance effects along the data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the display panel is made to have a larger screen and higher resolution, then the display quality is improved, but the load capacitance of data lines increases and the driving period becomes shorter
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency variable rather than constant. The clock signal frequency is dynamically adjusted based on the scanning line number, being higher for scanning lines closer to the data driver and lower for scanning lines farther away. This dynamic frequency adjustment compensates for the increasing load capacitance effect along the data lines, allowing the display panel to achieve high resolution and large screen while maintaining uniform voltage writing across all pixel units.
2Speed
If the load capacitance of data line increases and driving period shortens, then the selection period becomes shorter, but the signal waveform has more rounded rising edge and voltage level cannot be reached
Solution Approach 1:
The patent applies parameter changes by modifying the clock signal frequency parameter according to the scanning line position. Specifically, the clock signal frequency is set to decrease as the scanning line number increases (moving farther from the data driver). This parameter change compensates for the RC time constant effect caused by increasing load capacitance, ensuring that the voltage level is properly reached in pixel units regardless of their position on the display panel.
3Reliability
If the rising edge of signal waveform has rounded edge due to data line impedance, then the voltage level cannot be reached within data period, but luminance unevenness occurs
Solution Approach 1:
The patent applies local quality by implementing different clock signal frequencies for different scanning lines based on their local characteristics. Scanning lines closer to the data driver receive higher clock frequencies, while scanning lines farther away receive lower clock frequencies. This local differentiation compensates for the varying impedance effects along different data lines, ensuring uniform voltage writing and eliminating luminance unevenness across the display panel.
4Productivity
If the pixel electrode charging rate varies across the panel due to impedance effects, then luminance unevenness occurs, but uniform display is desired
Solution Approach 1:
The patent applies feedback by using the scanning line number as a feedback parameter to adjust the clock signal frequency. The system monitors the position of each scanning line and automatically adjusts the corresponding clock frequency to compensate for impedance effects. This feedback mechanism ensures that all pixel units, regardless of their position, achieve the same charging rate and display uniform luminance.
Data Source
AI summary
A display apparatus includes: a display panel; a gate driver that provides, to a plurality of scanning lines, scanning pulse signals for controlling pixel switches to be ON in a selection period corresponding to a pulse width thereof; a data driver that provides gradation voltage signals to a plurality of data lines; and a display controller that provides a modulated clock signal having a frequency that changes at a predetermined rate in one frame period. The gate driver sequentially provides the scanning pulse signals each having a pulse width reflecting to a clock cycle of the modulated clock signal in a predetermined order corresponding to distances from the data driver to the plurality of scanning lines. The data driver provides the gradation voltage signals in the order of providing the scanning pulse signals for every data period corresponding to the clock cycle of the modulated clock signal.