Display Controller RAM Redundancy via Unused Address Space
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Solution Overview
Problem
In liquid crystal display controllers, the existing RAM storage capacity is limited by the size of the display screen, leading to yield deterioration due to defects and increased chip cost, and the integration of redundancy circuits complicates chip design and size reduction.
Innovation Solution
A display control semiconductor integrated circuit with a fuse circuit for setting defect addresses and a comparing circuit to replace input addresses with spare memory addresses, utilizing unused address spaces for redundancy, eliminating the need for separate control circuits and reducing chip area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage capacity of the built-in RAM is increased to repair defective bits, then the yield is improved, but the chip area increases and chip cost increases
Solution Approach 1:
The patent utilizes the address space dimension to store redundancy information. Instead of adding physical memory cells in the traditional sense, the invention uses unused address spaces (high-order address bits) to encode redundancy control signals, thereby achieving defect repair functionality without increasing the physical chip area occupied by RAM cells.
Solution Approach 2:
The patent makes the address decoder and control circuits serve multiple functions: they not only decode normal address signals for reading/writing display data but also interpret high-order address bits as redundancy control signals. This multi-functionality allows the same hardware circuits to handle both normal operation and defect repair modes without requiring separate dedicated circuits.
2Reliability
If a redundancy circuit is provided to repair defective bits, then the yield is improved, but the device complexity increases
Solution Approach 1:
The patent makes the address decoder and control circuits serve multiple functions: they not only decode normal address signals for reading/writing display data but also interpret high-order address bits as redundancy control signals. This multi-functionality allows the same hardware circuits to handle both normal operation and defect repair modes without requiring separate dedicated circuits.
Solution Approach 2:
The patent implements self-service by using the address signals themselves (specifically the high-order bits) to control the redundancy function. The system automatically detects when redundancy should be activated based on the address pattern, and the control circuits automatically switch between normal and redundancy modes without requiring external intervention or complex control logic.
3Reliability
If separate control circuits are provided for normal memory and spare memory access, then the redundancy function is improved, but the chip area increases
Solution Approach 1:
The patent makes the address decoder and control circuits serve multiple functions: they not only decode normal address signals for reading/writing display data but also interpret high-order address bits as redundancy control signals. This multi-functionality allows the same hardware circuits to handle both normal operation and defect repair modes without requiring separate dedicated circuits.
Data Source
AI summary
The present invention provides a display control semiconductor integrated circuit having therein a RAM, capable of repairing a defective bit included in the RAM and improving the yield without significantly increasing the occupation area. A liquid crystal controller/driver in which a RAM for storing display data is provided in a chip and the storage capacity of the built-in RAM is determined according to the size of a display screen of a liquid crystal panel to be driven, includes a fuse circuit for setting a defect address, and a comparing circuit for comparing the defect address set in the fuse circuit with an input address. The liquid crystal controller/driver also has a redundant circuit, when the addresses match each other, for replacing the input address with an address that instructs the spare memory area and supplying the address to an address decoder.