Display Controller Video Sync Using External Clock

Solution Overview

Problem

Existing display controllers face challenges in generating video sync signals efficiently, as dedicated phase-locked loops (PLLs) lead to continuous power consumption and increased chip size, while fractional dividers require additional components and impose constraints on clock performance.

Innovation Solution

A display controller that generates video sync signals using an external clock, eliminating the need for dedicated PLLs and fractional dividers by utilizing an initializer and sync signal generation circuit to count and compare external clock cycles with setting values, thereby generating horizontal and vertical sync signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated phase-locked loop (PLL) is used to generate the clock for video sync signal, then the video sync signal can be generated with correct timing, but continuous power consumption occurs and the overall chip size increases

Engineering Contradiction:

Improvevideo sync signal timing accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The external clock signal, originally intended for a different purpose (such as display interface data transmission), is repurposed to generate the video sync signal. The display controller reuses this existing clock resource instead of requiring a dedicated PLL, thereby achieving multi-functionality of the clock signal and eliminating continuous power consumption associated with dedicated clock generation circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The video sync signal generation function is extracted from the dedicated PLL circuit and relocated to the display controller. By taking out the sync signal generation task from the clock generation subsystem and implementing it within the display controller using the external clock, the patent eliminates the need for continuous operation of dedicated PLL circuits.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If a dedicated phase-locked loop (PLL) is used to generate the clock for video sync signal, then the video sync signal can be generated with correct timing, but the area occupied by the dedicated PLL increases

Engineering Contradiction:

Improvevideo sync signal timing accuracyVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The external clock signal, originally intended for a different purpose (such as display interface data transmission), is repurposed to generate the video sync signal. The display controller reuses this existing clock resource instead of requiring a dedicated PLL, thereby achieving multi-functionality of the clock signal and eliminating continuous power consumption associated with dedicated clock generation circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The video sync signal generation function is extracted from the dedicated PLL circuit and relocated to the display controller. By taking out the sync signal generation task from the clock generation subsystem and implementing it within the display controller using the external clock, the patent eliminates the need for continuous operation of dedicated PLL circuits.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If a fractional divider is used to generate the clock for video sync signal, then the clock can be generated, but an additional first-in first-out (FIFO) is required and constraints irrelevant to the performance of a clock need to be dealt with

Engineering Contradiction:

Improveclock generationVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The external clock signal, originally intended for a different purpose (such as display interface data transmission), is repurposed to generate the video sync signal. The display controller reuses this existing clock resource instead of requiring a dedicated PLL, thereby achieving multi-functionality of the clock signal and eliminating continuous power consumption associated with dedicated clock generation circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The video sync signal generation function is extracted from the dedicated PLL circuit and relocated to the display controller. By taking out the sync signal generation task from the clock generation subsystem and implementing it within the display controller using the external clock, the patent eliminates the need for continuous operation of dedicated PLL circuits.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS10554865B2Display controller for generating video sync signal using external clock, an application processor including the controller, and an electronic system including the controller

Publication Date: 2020.02.04 SAMSUNG ELECTRONICS CO LTD

AI summary

In a display controller for generating a video sync signal using an external clock, he display controller includes an initializer configured to initialize an internal parameter in response to a frame start signal. A sync signal generation circuit is configured to count the external clock, increase the internal parameter, and generate the video sync signal according to a result of comparing the internal parameter that has been increased with a setting value. An original use of the external clock may not be generating the video sync signal.