Display Data Transmission Without Clock Bits Using Bit Inversion
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Solution Overview
Problem
Existing data transmitting systems in display apparatuses require additional clock signals and bits, which increase power consumption, reduce data bandwidth, and lead to higher manufacturing costs and increased electromagnetic interference.
Innovation Solution
A data transmitting system that transmits data without an additional clock signal or bit by using a method where the transmitter inverts bits of unit data when the last bit of the first unit data and the first bit of the second unit data have the same value, and uses a restoring circuit to correct the inverted bits, thereby eliminating the need for clock bits in the data signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock embedded method is used to transmit data signals at high frequency, then data transmission reliability is improved, but power consumption increases and data bandwidth decreases
Solution Approach 1:
The patent extracts and removes the clock signal from the data transmission system. Instead of embedding clock bits within the data signal, the system uses the inherent transition characteristics of the data signal itself (edges between consecutive data bits) to achieve synchronization, thereby eliminating the power consumption and bandwidth overhead associated with clock signal transmission.
Solution Approach 2:
The patent makes the data signal serve multiple functions: it simultaneously carries both data information and synchronization information. By detecting edge transitions in the data signal, the receiver can extract timing information without requiring a separate clock signal, thus achieving multi-functionality with a single signal.
2Measurement precision
If additional clock bits are included in the data signal, then data transmission accuracy is improved, but data bandwidth decreases
Solution Approach 1:
The patent removes dedicated clock bits from the data signal structure. Instead, it utilizes the natural transition edges between consecutive data bits as synchronization markers, thereby preserving the full data bandwidth while maintaining transmission accuracy through edge-based timing detection.
Solution Approach 2:
The data signal bits serve dual purposes: they convey both the actual data information and the timing/synchronization information. Each data bit transition provides both data value and clock edge information, eliminating the need for separate clock bits and maximizing data bandwidth utilization.
3Manufacturing precision
If more driving blocks are used to support high resolution display, then display quality is improved, but manufacturing cost increases
Solution Approach 1:
The patent eliminates the need for additional clock driving blocks by extracting clock functionality from the data signal itself. This reduction in required driving blocks directly lowers manufacturing costs while maintaining support for high resolution displays through efficient data transmission.
Solution Approach 2:
The timing controller's data output block performs both data driving and clock signal generation functions simultaneously. By making the data signal self-synchronizing through edge detection, the system reduces the number of separate driving blocks needed, thereby reducing manufacturing complexity and cost.
4Reliability
If clock signal transmission is implemented, then data synchronization is improved, but electromagnetic interference increases
Solution Approach 1:
The patent removes the separate clock signal transmission path that generates electromagnetic interference. Instead, synchronization is achieved by detecting edges in the data signal itself, thereby eliminating the source of EMI while maintaining robust data synchronization.
Solution Approach 2:
The data signal simultaneously provides both data transmission and synchronization functions. By using the data signal's own transitions as clock edges, the system avoids generating additional electromagnetic interference from separate clock signal lines while maintaining accurate synchronization.
Data Source
AI summary
A data transmitting system includes a transmitter configured to transmit first unit data having a first bit length and second unit data sequentially with the first unit data and having the first bit length and a receiver configured to receive the first unit data and the second unit data. The transmitter is configured to transmit the second unit data to the receiver when a last bit of the first unit data and a first bit of the second unit data have different values and to invert the first bit of the second unit data and transmit the second unit data having the inverted first bit to the receiver when the last bit of the first unit data and the first bit of the second unit data have the same value.