Display Device Data Distribution Circuit with Non-Rectilinear Transistor Gaps

By stacking transistors vertically in multiple layers, the horizontal gap area between transistors can be reduced while still maintaining adequate electrical isolation and preventing short circuits. The vertical stacking allows the data distribution circuit to occupy a smaller horizontal area, thus reducing the overall display panel size while preserving reliability through proper vertical spacing and insulation between layers.

Multiple transistor layers are nested vertically within a compact footprint area. Each layer of transistors is positioned directly above or below adjacent layers, creating a nested three-dimensional structure. This nesting approach maximizes the use of vertical space, allowing more transistors to be packed into a smaller horizontal area, thereby reducing the data distribution circuit size while maintaining adequate isolation between transistors through vertical spacing.

The gate insulation layer and interlayer insulation layers serve dual functions: they provide electrical isolation between transistor components and simultaneously act as light blocking structures. By making these insulation layers sufficiently thick and using appropriate materials with high light absorption coefficients, the patent prevents light from reaching the semiconductor layer and causing leakage currents, while avoiding the need for separate dedicated light blocking structures that would increase device complexity.

The light blocking function is merged with the existing insulation layers in the transistor structure. Rather than adding separate light blocking layers, the patent combines the light blocking capability with the gate insulation layer and interlayer insulation layers that are already present for electrical isolation. This merging approach achieves light blocking to prevent leakage currents without increasing device complexity, as the same structural elements perform both functions.