Display Data Driver Clock Embedded Signal Noise Control
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Solution Overview
Problem
Display apparatuses, such as flat panel displays, generate noise that degrades the communication performance of electronic systems, leading to receiver desensitization and reduced display quality.
Innovation Solution
A method for operating a display apparatus that involves generating a clock embedded data signal by combining the clock signal with the output image data and controlling the voltage offset and slew rate of this signal, reducing harmonic noise without changing the frequency, and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal is combined with image data to form a clock embedded data signal for transmission, then data transmission efficiency is improved, but harmonic noise increases degrading communication performance
Solution Approach 1:
The patent applies periodic action by adjusting the voltage offset and slew rate of the clock embedded data signal specifically during blank periods when no real image data is transmitted. This periodic modification of signal characteristics during non-critical transmission intervals reduces harmonic noise without affecting the overall data transmission efficiency, as the active periods maintain normal signal operation
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the voltage offset and slew rate parameters of the clock embedded data signal. During blank periods, these parameters are modified to reduce harmonic noise generation, while during active periods containing real image data, the parameters are maintained at normal levels to ensure proper data transmission
2Reliability
If the voltage offset and slew rate of the clock embedded data signal are adjusted to reduce harmonic noise, then communication performance is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing voltage offset and slew rate adjustments only during blank periods when no real image data is transmitted. This time-selective approach allows communication performance to be optimized during non-critical intervals without continuously increasing power consumption, as the adjustments are temporarily applied only when needed
Solution Approach 2:
The patent applies preliminary action by adjusting voltage offset and slew rate parameters during blank periods before the next active period begins. This preparatory adjustment during idle time reduces harmonic noise that would otherwise affect communication performance during upcoming active periods, without requiring continuous power expenditure
3Object-generated harmful factors
If the voltage offset of the clock embedded data signal is adjusted during blank periods, then harmonic noise is reduced, but signal quality during active periods may be affected
Solution Approach 1:
The patent applies periodic action by restricting voltage offset adjustments to blank periods only, when no real image data is being transmitted. This temporal separation ensures that signal quality during active periods remains unaffected, as the adjustments are temporarily applied only during intervals when signal transmission is not critical
Solution Approach 2:
The patent applies local quality by making voltage offset adjustments specifically during blank periods when local signal transmission requirements are minimal. This localized adjustment approach allows harmonic noise reduction in specific time intervals without compromising the overall signal quality during active periods when full signal integrity is required
Data Source
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AI summary
In a method of operating a display apparatus, during a first period (T1) in which image data is provided to a data driver, a clock embedded data signal having an output differential voltage ("VOD") set to a first voltage value (VV1)) is applied to the data driver. The VOD of the clock embedded data signal relates to a voltage difference between a high level and a low level of the clock embedded data signal. During a second period (T2) in which the image data is not provided to the data driver, the VOD of the clock embedded data signal applied to the data driver is changed to a second voltage value smaller than the first voltage value (VV2).