Display Data Driver Clock Training for Frame Frequency Adaptability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices using USI-T or USI-GF interfaces face operation errors due to lock sensing errors when frame frequencies change, as the data driver fails to recover the correct clock signal, leading to unlocking of the internal clock signal.
Innovation Solution
A display device with a controller providing a clock-embedded data signal including a training pattern in both active and blank periods, where the data driver recovers image data in the active period and performs training operations using the training pattern in the blank period, utilizing a shared back channel to inform the controller of lock states and using specific modulation periods for the training clock signals to prevent lock sensing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the frame frequency is drastically changed, then the display device can adapt to different frame rates, but a lock sensing error occurs where the data driver incorrectly determines the recovered clock signal is locked when it is actually unlocked
Solution Approach 1:
The patent applies preliminary action by performing a training operation before normal data transmission. During the blank period, the controller sends a training pattern (first data signal) that causes the data driver to perform clock training, establishing the correct lock state before actual image data transmission begins. This preliminary training prevents lock sensing errors when frame frequency changes occur.
Solution Approach 2:
The patent implements feedback through a back channel that transmits the second data signal from the data driver to the controller. This feedback mechanism allows the controller to verify whether the data driver has correctly determined the lock state of the recovered clock signal. If the lock state is incorrect, the controller can detect this through the feedback and take corrective action, ensuring reliable operation even when frame frequency changes.
2Device complexity
If a single modulation period is used for the training clock signal, then the training operation is simple, but it cannot accurately determine the lock state when frame frequency changes drastically
Solution Approach 1:
The patent applies segmentation by dividing the training clock signal into two distinct modulation periods: a first modulation period for initial training and a second modulation period for lock state verification. This segmentation allows each modulation period to serve a specific function - the first establishes the clock signal parameters while the second verifies proper locking, thereby improving measurement precision without excessive complexity.
Solution Approach 2:
The patent uses periodic action by employing two different modulation periods in sequence during the training phase. The training clock signal alternates between the first modulation period and the second modulation period, allowing the system to perform different training functions at different time intervals. This periodic variation in modulation periods enables accurate lock state determination while maintaining manageable signal structure.
Data Source
AI summary
A display device includes a display panel including a plurality of pixels, a controller for providing a clock-embedded data signal including image data in an active period and including a training pattern in a blank period, and a data driver for recovering the image data from the clock-embedded data signal based on an internal clock signal to provide data voltages corresponding to the image data to the plurality of pixels in the active period, and to perform a training operation for the internal clock signal using the training pattern included in the clock-embedded data signal in the blank period. The training pattern in the blank period includes a first training clock signal modulated with a first modulation period during a first time, and includes a second training clock signal modulated with a second modulation period different from the first modulation period after the first time.


