Display Data Driver RC Delay Compensation
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Solution Overview
Problem
In liquid crystal display (LCD) apparatuses, the resistive-capacitive (RC) delay in gate signals causes timing issues due to the relative position of data lines, affecting the display quality by delaying gate signals, which is not effectively addressed by existing technologies.
Innovation Solution
A display apparatus with a data driver that includes multiple data line groups with different delay times for outputting data voltages, synchronized with multi-phase clock signals, and a timing controller generating delay control signals to manage these delays, ensuring accurate synchronization and compensation for RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data voltages are output to multiple data line groups with the same timing, then the device complexity is low, but the RC delay in gate signals causes timing issues affecting display quality
Solution Approach 1:
The patent segments the data lines into multiple data line groups (first through fourth data line groups) and applies different delay times to each group. The data driver includes multiple data driving circuits that output data voltages to different data line groups with different delay times, thereby compensating for RC delay effects and improving display quality without requiring complete system redesign
Solution Approach 2:
The patent applies different delay characteristics to different data line groups based on their specific positions and RC delay characteristics. Each data line group receives data voltages with delay times specifically tailored to its RC delay properties, rather than applying a uniform delay to all data lines. This localized approach optimizes compensation effectiveness while managing device complexity
2Manufacturing precision
If different delay times are applied to different data line groups, then the RC delay is compensated and display quality improves, but the device complexity increases due to multiple data driving circuits and delay control mechanisms
Solution Approach 1:
The patent employs periodic clock signals (first clock signal and second clock signal) to control the output timing of data voltages to different data line groups. By using phase-differentiated clock signals, the system achieves different effective delay times for different data line groups through periodic sampling and holding operations, reducing the need for complex continuous delay circuits
Solution Approach 2:
The patent introduces a timing controller as an intermediary component that generates delay control signals to coordinate the operation of multiple data driving circuits. The timing controller manages the complex timing relationships between different data line groups by providing centralized control, thereby reducing the complexity burden on individual data driving circuits
3Ease of operation
If gate signals are delayed due to RC delay, then the signal transmission is simplified, but the timing accuracy deteriorates affecting image display
Solution Approach 1:
The patent applies preliminary delay compensation to data voltages before they are transmitted to the data lines. By calculating and applying the appropriate delay time to each data line group in advance (based on their RC delay characteristics), the system pre-corrects for the expected delay, ensuring that data voltages arrive at the pixels at the correct timing despite RC delay effects during transmission
Data Source
AI summary
A display apparatus includes a display panel and a data driver. The display panel is configured to display an image and includes first through fourth data line groups. The first and second data line groups are adjacent to each other, and the third and fourth data line groups are adjacent to each other. The data driver includes a first data driving circuit configured to output first data voltages to the second data line group later than to the first data line group by a first delay time, and configured to output second data voltages to the fourth data line group later than to the third data line group by a second delay time that is different from the first delay time.