Multi-Level Display Data Driver Reducing EMI and Wiring

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Solution Overview

Problem

High-speed clock signals and increased electromagnetic interference (EMI) in flat panel display systems lead to signal skew and jitter issues during data transmission, particularly with the Point-to-Point Differential Signaling (PPDS) method, which requires multiple clock lines and separate circuits for skew compensation.

Innovation Solution

A display system that transmits serialized multi-level data with an embedded clock signal using a single or dual wiring, reducing the number of wirings and EMI by employing a multi-level signaling scheme where the data signal has at least four levels, and optionally inserting dummy data to maintain signal integrity and reduce jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a high-speed clock signal is used to transmit data at high speed, then data transmission speed is improved, but electromagnetic interference (EMI) increases

Engineering Contradiction:
Improvedata transmission speedVSAvoidelectromagnetic interference (EMI)
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent changes the signal level parameter from conventional 2-level signaling to 4-level or higher multi-level signaling. This allows transmitting more bits per clock cycle (e.g., 2 bits per level transition), effectively doubling the data transmission rate without increasing clock frequency, thereby reducing EMI while maintaining high-speed performance

Inventive Principle:
Principle #35Parameter changes

2Reliability

If separate clock lines are connected to all data drivers to eliminate signal skew, then data transmission reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the clock signal transmission with the data signal transmission by embedding the clock within the data stream using multi-level signaling. The clock information is encoded in the transitions between different signal levels, eliminating the need for separate clock lines and reducing device complexity while maintaining synchronization reliability

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If the number of data lines is increased to achieve high resolution, then display quality is improved, but EMI increases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidelectromagnetic interference (EMI)
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent changes the signaling parameter from 2-level to 4-level or higher multi-level signaling, which reduces the number of data lines required. For example, 4-level signaling transmits 2 bits per line instead of 1 bit per line, effectively halving the number of lines needed for the same resolution, thereby reducing EMI while maintaining display quality

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8149253B2Display, timing controller and data driver for transmitting serialized multi-level data signal
Publication Date: 2012.04.03 ANAPASS
  • US8149253B2 patent drawing
  • US8149253B2 patent drawing
  • US8149253B2 patent drawing

AI summary

The present invention relates to a display, a timing controller and a data driver for transmitting a serialized multi-level data signal, and more particularly to a display, a timing controller and a data driver for transmitting a serialized multi-level data signal for reducing the number of wirings between the timing controller and the data driver, and for reducing an EMI component. The display of the present invention comprises a display panel, a scan driver, a timing controller and a plurality of data drivers, wherein the timing controller transmits a transmission signal including a serialized data signal to one of the plurality of the data drivers, wherein a level of the data signal is selected from at least four different levels according to a value of a data having a length of at least two bits, and wherein the data driver restores the data from the transmitted transmission signal.