Display Data Driving Circuit Dual Clock Signal Power Optimization
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Solution Overview
Problem
Display devices face increased unnecessary power consumption due to inefficiencies in power management, particularly in eco-friendly and mobile environments, where reducing power usage is crucial for battery efficiency and environmental sustainability.
Innovation Solution
A display device, display controller, and data driving circuit configuration that utilizes a dual clock signal system, where a first type clock signal toggles voltage levels and a second type clock signal maintains a constant voltage, to control data voltage output based on data comparisons, thereby optimizing power usage by minimizing static current during no data transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single clock signal is used for data driving, then the device complexity is low, but power consumption increases due to unnecessary operations during static areas
Solution Approach 1:
The clock signal system is segmented into two distinct types: a first clock signal for dynamic areas requiring data transitions, and a second clock signal for static areas where data remains unchanged. This segmentation allows the system to select the appropriate clock signal based on the display content, reducing unnecessary operations and power consumption in static regions.
Solution Approach 2:
The system dynamically switches between two clock signal modes based on the detection of data transitions. When data changes are detected, the first clock signal is applied; when no changes are detected, the second clock signal is applied. This dynamic adaptation optimizes power consumption while maintaining display functionality.
2Loss of energy
If continuous data updating is performed, then the display quality is maintained, but power consumption increases due to unnecessary updates in static areas
Solution Approach 1:
The system incorporates a feedback mechanism that detects whether data transitions occur between frames. Based on this feedback, the control circuit selectively applies the first or second clock signal. This feedback-driven approach ensures that display quality is maintained when needed while reducing power consumption when the display content remains static.
Solution Approach 2:
The system changes the operational parameter (clock signal type) based on the detected data transition state. By switching between two clock signal parameters, the system optimizes the balance between display quality and power consumption, applying full updating only when necessary.
3Loss of energy
If a dual clock signal system is implemented, then power consumption is reduced in static areas, but the device complexity increases
Solution Approach 1:
A control circuit acts as an intermediary between the data input and the clock signal distribution. This intermediary detects data transitions and automatically selects the appropriate clock signal type, managing the complexity of the dual-clock system while enabling power savings. The control circuit serves as a mediator that simplifies the overall system architecture by centralizing the decision-making logic.
Data Source
AI summary
A display device, a display controller, a data driving circuit, and a low power driving method that are capable of preventing undesirable current in the data driving circuit from being caused and reducing power consumption by using different types of clock signals needed for data storing processing according to whether there occurs no data transition or there occurs a data transition.