Flat Panel Display Data Interface Clock Embedding
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Solution Overview
Problem
Flat panel display devices face issues with electromagnetic interference (EMI) and unstable data sampling due to increased data transfer frequencies and the number of data transfer lines, which complicates the design of printed circuit boards and leads to erroneous data sampling and clock delays.
Innovation Solution
The apparatus and method for data interface in flat panel display devices embed clocks within digital data and use a transmitter unit in the timing controller to transmit clock-embedded data, along with a clock enable signal, to receiver units in data integrated circuits, allowing for accurate clock detection and reduced transfer lines by converting data into differential signals and using clock mask signals for stable clock detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer frequency and number of data transfer lines are increased to achieve higher resolution and larger size display, then data transfer capability is improved, but electromagnetic interference increases causing unstable operation
Solution Approach 1:
The patent merges the clock signal transmission with data transmission by embedding the clock signal within the data signal itself. This is achieved through a serializer that converts parallel data into serial data while incorporating clock information, eliminating the need for separate clock transfer lines and reducing the overall number of transfer lines that generate electromagnetic interference
Solution Approach 2:
The patent extracts the clock signal from being a separate physical transmission entity and instead embeds it within the data stream. The receiver unit separates and detects the embedded clock from the data signal, allowing clock functionality to be maintained without requiring dedicated clock lines that contribute to EMI
2Object-affected harmful factors
If a differential voltage method is used for data interface to reduce EMI and power consumption, then EMI and power consumption are reduced, but the number of data transfer lines increases causing distortion and design difficulty
Solution Approach 1:
The patent combines multiple functions into a single data transmission channel. By embedding clock signals within the data stream and using the same physical transfer lines for both data and clock transmission, the system reduces the total number of lines required while maintaining differential signaling benefits for EMI and power consumption reduction
Solution Approach 2:
The data transfer lines are given multiple functions: they transmit both data signals and embedded clock signals. This multi-functionality allows the system to maintain accurate timing and data transmission without requiring separate dedicated lines for each function, thereby reducing overall line count and complexity
3Device complexity
If a multi-drop system is used to transfer clocks and data to multiple data ICs, then device complexity is reduced, but clock delay increases causing inaccurate data sampling
Solution Approach 1:
The patent segments the data transmission into individual point-to-point connections from the timing controller to each data IC. Each data IC receives its own embedded clock signal directly from the timing controller through dedicated transfer lines, eliminating the cumulative clock delay problem of multi-drop systems where clock signals are shared across multiple devices in sequence
Solution Approach 2:
The clock signal is embedded within the data signal before transmission, and the receiver unit separates and detects this embedded clock in advance of data sampling. This preliminary extraction and detection of the clock signal ensures accurate timing reference is available at each data IC without being affected by delays from other devices in the system
Data Source
AI summary
An apparatus and method for data interface of a flat panel display device, which is capable of transferring clocks in a state, in which the clocks are embedded in digital data, thereby reducing the number of transfer lines, is disclosed. The apparatus includes a transmitter unit built in a timing controller, to transmit transfer data with an embedding clock embedded between successive pieces of data, and a clock enable signal to indicate the embedding clock, and receiver units respectively built in a plurality of data integrated circuits connected to the timing controller, to separate and detect the embedding clock and the data from the transfer data, in response to the clock enable signal.