Display Apparatus Data Line Reduction via Sequential Gate Activation
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Solution Overview
Problem
As display apparatuses are manufactured with increased resolution and larger screen sizes, the need for more compact and lighter components leads to an increase in the number of data lines and gate lines, resulting in larger sizes and deteriorated image quality due to parasitic capacitances and flickering issues, such as vertical stains.
Innovation Solution
A display apparatus design where data signals are provided to two adjacent pixels along a gate line using one data line, reducing the required number of data lines and gate lines, and applying gate voltages sequentially to minimize kickback voltages and vertical flickering lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of data lines and gate lines is increased to achieve increased resolution, then the resolution is improved, but the size of the display apparatus is substantially increased
Solution Approach 1:
The patent merges the functions of multiple data lines by enabling a single data line to serve multiple pixels through time-division multiplexing. The gate driver sequentially activates different gate lines to access the same data line for different pixels, effectively combining multiple data transmission functions into a single physical line, thereby reducing the overall number of lines required and the display apparatus size.
Solution Approach 2:
The patent introduces a temporal dimension to data transmission by sequentially activating gate lines over time. Instead of requiring simultaneous data transmission through multiple parallel data lines, the system uses time-division multiplexing where one data line serves multiple pixels in sequence across different time periods, effectively adding a time dimension to resolve the spatial constraint.
2Measurement precision
If the number of gate lines is increased to achieve increased resolution, then the resolution is improved, but vertical flickering lines and image quality deteriorate due to parasitic capacitances
Solution Approach 1:
The patent applies preliminary action by sequentially activating gate lines in a predetermined order before data transmission occurs. The gate driver activates gate lines in a specific sequence (e.g., from top to bottom or bottom to top) to establish voltage conditions beforehand, which minimizes parasitic capacitance effects and kickback voltages that would otherwise cause vertical flickering and image quality deterioration.
Solution Approach 2:
The patent employs periodic action through sequential gate line activation cycles. The gate driver repeatedly cycles through activating different gate lines in a predetermined sequence, creating a periodic scanning pattern that allows controlled voltage distribution across the display matrix. This periodic activation pattern minimizes simultaneous voltage conflicts and reduces parasitic capacitance-induced interference, thereby improving image quality while maintaining high resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains or improves resolution without increasing the display apparatus size, reduces vertical flickering lines, and enhances overall display quality by managing kickback voltages effectively.
Implementation Method 1
an alignment of liquid crystal molecules in the liquid crystal layer is controlled, and a polarization of incident light is thereby controlled
Implementation Method 2
voltages are applied to the electric field generating electrodes to generate an electric field between the pixel electrode and the common electrode
Data Source
AI summary
A display apparatus includes: a plurality of pixel blocks, each pixel block of the plurality of pixel blocks including a first pixel electrode connected to a first switching element and a second pixel electrode connected to a second switching element; gate lines which extend along a first direction and include a first gate line connected to the first switching element and a second gate line connected to the second switching element; and data lines which extend along a second direction intersecting the first direction. A gate voltage is applied to the first gate line before the second gate line, and the first pixel electrode of each of the pixel blocks displays a same color.