Display Apparatus Data Line Arrangement for Small Pixel Pitch

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Solution Overview

Problem

Conventional display apparatus designs face challenges in achieving small pixel pitch due to limitations in patterning metal layers for data lines and conductive pads, leading to narrow spaces between semiconductor portions and reduced pixel electrode widths, which affect display quality and reliability.

Innovation Solution

The proposed display apparatus design features a substrate with gate lines and data lines extending in different directions, with conductive pads positioned between these lines, allowing for increased spacing and flexibility in pixel electrode sizes, enabling the formation of pixels with smaller pixel pitch by using multiple data lines at different horizontal levels and misaligned contacts to improve electrical connections without compromising aperture ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the widths of data lines and conductive pads are decreased to achieve small pixel pitch, then the pixel pitch is reduced, but the manufacturing precision deteriorates due to process limitations in patterning the second metal layer

Engineering Contradiction:
Improvepixel pitchVSAvoidpatterning precision
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent introduces a third metal layer above the second metal layer to form data lines and conductive pads. This vertical dimensionality change allows the data lines and conductive pads to be formed at different heights, enabling small pixel pitch while maintaining adequate line widths for manufacturable patterning precision. The third metal layer's data lines can extend beyond the second metal layer's conductive pads, achieving both compact pixel layout and reliable electrical connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of stationary object

If the width of pixel electrode is reduced to achieve small pixel pitch, then the pixel pitch is reduced, but the aperture ratio deteriorates

Engineering Contradiction:
Improvepixel pitchVSAvoidaperture ratio
Core Design Contradiction:
Length of stationary objectVSArea of stationary object

Solution Approach 1:

By forming the pixel electrode in the third metal layer at a higher level, the patent enables the pixel electrode to extend more freely in the horizontal plane without being constrained by the narrow spacing requirements of lower-layer conductors. This vertical separation allows the pixel electrode to maintain a larger effective area for light transmission while the overall pixel pitch remains small, thus preserving high aperture ratio despite compact pixel dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If multiple data lines are added at different horizontal levels to improve electrical connections, then the electrical connectivity is improved, but the device complexity increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidlayer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the electrical connection function across multiple metal layers, with the second metal layer forming conductive pads and the third metal layer forming data lines. This segmentation allows each layer to be optimized independently for its specific function, improving electrical connectivity while distributing the complexity across separate fabrication stages rather than requiring all elements to coexist in a single plane.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10453868B2Display apparatus
Publication Date: 2019.10.22 INNOLUX CORP
  • US10453868B2 patent drawing
  • US10453868B2 patent drawing
  • US10453868B2 patent drawing

AI summary

A display apparatus includes a substrate, a gate line disposed on the substrate and extending along a first direction, a gate insulating layer covering the gate line, a first data line disposed on the gate insulating layer and extending along a second direction different from the first direction, a first insulating layer covering the first data line, and a second data line disposed between the substrate and the gate insulating layer, or disposed on the first insulating layer, wherein the second data line extends along the second direction, and both of the first data line and the second data line intersect with the gate line.